decoder3_8.vhd

来自「decoder3_8实现了FPGA或CPLD 实现3-8译码器的功能」· VHDL 代码 · 共 36 行

LIBRARY IEEE;
USE ieee.std_logic_1164.all;

ENTITY decoder3_8 IS

	PORT
	(
				s		: IN	STD_LOGIC_VECTOR(2 DOWNTO 0 );
		g1,g2a,g2b	: IN	STD_LOGIC;
				d: OUT 		STD_LOGIC_VECTOR(7 DOWNTO 0 ));
	
END decoder3_8;

ARCHITECTURE deco_arch OF decoder3_8 IS	
BEGIN
	PROCESS (s,g1,g2a,g2b)
	BEGIN	
		IF (g1='1' AND g2a='0' AND g2b='0' ) THEN		
			CASE s IS
 			WHEN "000"=>d<="11111110";
		    WHEN "001"=>d<="11111101";
			WHEN "010"=>d<="11111011";
			WHEN "011"=>d<="11110111";
			WHEN "100"=>d<="11101111";
			WHEN "101"=>d<="11011111";
			WHEN "110"=>d<="10111111";
			WHEN "111"=>d<="01111111";
			WHEN OTHERS=>d<="XXXXXXXX";
		END  CASE;
    ELSE
    d<="11111111";
    END IF;
	END PROCESS;		
END  deco_arch;