m4.vhd

使用VHDL语言产生4M分频

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m4 is
port(clk_in:in std_logic;
     clk_out:out std_logic);
end m4;
architecture com of m4 is
signal count:std_logic_vector(21 downto 0);
begin
 process(clk_in)
  begin
  if clk_in'event and clk_in='1' then
    if count<"111111111111111111111" then
       count<=count+1;
       clk_out<='0';
    else count<="0000000000000000000000";
         clk_out<='1';
    end if;
   end if;
  end process;
end com;