📄 mcu8951.map.rpt
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Analysis & Synthesis report for MCU8951
Wed Mar 18 18:44:58 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Default Parameter Settings
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Logic Cells Representing Combinational Loops
10. Registers Removed During Synthesis
11. Removed Registers Triggering Further Register Optimizations
12. General Register Statistics
13. Inverted Register Statistics
14. Multiplexer Restructuring Statistics (Restructuring Performed)
15. Source assignments for CPU8051V1:inst
16. Source assignments for ram256:inst6|altsyncram:altsyncram_component|altsyncram_vbg1:auto_generated|altsyncram_hob2:altsyncram1
17. Source assignments for ram256:inst6|altsyncram:altsyncram_component|altsyncram_vbg1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
18. Source assignments for rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_kod1:auto_generated|altsyncram_22d2:altsyncram1
19. Source assignments for rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_kod1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
20. Source assignments for sld_hub:sld_hub_inst
21. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
22. Parameter Settings for User Entity Instance: pll50:inst17|altpll:altpll_component
23. Parameter Settings for User Entity Instance: ram256:inst6|altsyncram:altsyncram_component
24. Parameter Settings for User Entity Instance: ram256:inst6|altsyncram:altsyncram_component|altsyncram_vbg1:auto_generated|sld_mod_ram_rom:mgl_prim2
25. Parameter Settings for User Entity Instance: rom4kb:inst5|altsyncram:altsyncram_component
26. Parameter Settings for User Entity Instance: rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_kod1:auto_generated|sld_mod_ram_rom:mgl_prim2
27. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
28. In-System Memory Content Editor Settings
29. Analysis & Synthesis Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 18 18:44:58 2009 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; MCU8951 ;
; Top-level Entity Name ; MCU8951 ;
; Family ; Cyclone II ;
; Total logic elements ; 1,800 ;
; Total combinational functions ; 1,800 ;
; Dedicated logic registers ; 684 ;
; Total registers ; 684 ;
; Total pins ; 17 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 34,816 ;
; Embedded Multiplier 9-bit elements ; 0 ;
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