spc.qsf

Alera 的8051 IP core的示例文件5个

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		SPC_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:38:44  MARCH 14, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VHDL_FILE ADSRAM.VHD
set_global_assignment -name VHDL_FILE ADSUART.VHD
set_global_assignment -name VHDL_FILE LPMRAM.vhd
set_global_assignment -name BDF_FILE SPC.bdf
set_global_assignment -name VHDL_FILE SUART.VHD
set_global_assignment -name VHDL_FILE U_BAUD.VHD
set_global_assignment -name VHDL_FILE U_REC.VHD
set_global_assignment -name VHDL_FILE U_XMIT.VHD
set_global_assignment -name VHDL_FILE CNT8.vhd
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_parameter -name CYCLONEII_SAFE_WRITE "\"VERIFIED_SAFE\""

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_17 -to CLK
set_location_assignment PIN_57 -to RST
set_location_assignment PIN_87 -to RXD
set_location_assignment PIN_92 -to TXD

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name TOP_LEVEL_ENTITY SPC

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP2C5T144C8
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------

# -----------------
# start ENTITY(SPC)


	# -------------------------------------
	# start LOGICLOCK_REGION("Root Region")

		# LogicLock Region Assignments
		# ============================
		set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
		set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

	# end LOGICLOCK_REGION("Root Region")
	# -----------------------------------

# end ENTITY(SPC)
# ---------------

set_global_assignment -name VHDL_FILE KONXIN_EXP1.vhd
set_global_assignment -name BDF_FILE KONXIN1.bdf
set_global_assignment -name VHDL_FILE KXRAM.vhd
set_global_assignment -name VHDL_FILE CNT32B.vhd
set_global_assignment -name VHDL_FILE CNT8B.vhd
set_global_assignment -name VHDL_FILE MUX21S.vhd
set_global_assignment -name VHDL_FILE MUX41S.vhd
set_location_assignment PIN_65 -to S1
set_location_assignment PIN_67 -to S2
set_global_assignment -name VHDL_FILE reg8B.vhd