fifotop.tan.summary

基于FPGA编写的VHDL语言

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.883 ns
From           : rden
To             : ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg3
From Clock     : --
To Clock       : rd_clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.031 ns
From           : gray:inst|new_q[4]
To             : full
From Clock     : wr_clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.343 ns
From           : data[5]
To             : ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5
From Clock     : --
To Clock       : wr_clk
Failed Paths   : 0

Type           : Clock Setup: 'rd_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 96.02 MHz ( period = 10.414 ns )
From           : gray:inst6|new_q[2]
To             : ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg3
From Clock     : rd_clk
To Clock       : rd_clk
Failed Paths   : 0

Type           : Clock Setup: 'wr_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 104.12 MHz ( period = 9.604 ns )
From           : gray:inst|new_q[3]
To             : ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg7
From Clock     : wr_clk
To Clock       : wr_clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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