empty_cmp.vhd.bak

基于FPGA编写的VHDL语言

--empty_cmp.vhd
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity empty_cmp is
generic(n:integer :=4);
port(
    --
    wr_addr:in std_logic_vector(n-1 downto 0);
    --
    rd_addr:in std_logic_vector(n-1 downto 0);
    --
    empty :out std_logic
);
end empty_cmp;

architecture behave of empty_cmp is

begin
  empty<='1'when wr_addr(n-1 downto 0)= rd_addr(n-1 downto 0))
  else
   '0';
end behave;