📄 fifotop.map.rpt
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; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------+
; n ; 5 ; Signed Integer ;
+----------------+-------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: gray:inst ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------+
; n ; 5 ; Signed Integer ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ramdp:inst4|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Signed Integer ;
; WIDTHAD_A ; 4 ; Signed Integer ;
; NUMWORDS_A ; 16 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Signed Integer ;
; WIDTHAD_B ; 4 ; Signed Integer ;
; NUMWORDS_B ; 16 ; Signed Integer ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; CLOCK1 ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; M4K ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_puo1 ; Untyped ;
+------------------------------------+----------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: g2b:inst1 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------+
; n ; 5 ; Signed Integer ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: g2b:inst2 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------+
; n ; 5 ; Signed Integer ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
Info: Processing started: Tue Apr 21 21:27:05 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifotop -c fifotop
Info: Found 1 design units, including 1 entities, in source file fifotop.bdf
Info: Found entity 1: fifotop
Info: Elaborating entity "fifotop" for the top level hierarchy
Warning: Using design file full_empty.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: full_empty
Info: Elaborating entity "full_empty" for hierarchy "full_empty:inst3"
Warning: Using design file empty_cmp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: empty_cmp-behave
Info: Found entity 1: empty_cmp
Info: Elaborating entity "empty_cmp" for hierarchy "full_empty:inst3|empty_cmp:inst5"
Warning: Using design file g2b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: g2b-behave
Info: Found entity 1: g2b
Info: Elaborating entity "g2b" for hierarchy "full_empty:inst3|g2b:inst9"
Warning: Using design file sync.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: sync-behave
Info: Found entity 1: sync
Info: Elaborating entity "sync" for hierarchy "full_empty:inst3|sync:inst7"
Warning: Using design file full_cmp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: full_cmp-behave
Info: Found entity 1: full_cmp
Info: Elaborating entity "full_cmp" for hierarchy "full_empty:inst3|full_cmp:inst4"
Warning: Using design file gray.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: gray-behavioral
Info: Found entity 1: gray
Info: Elaborating entity "gray" for hierarchy "gray:inst6"
Warning: Using design file ramdp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: ramdp-SYN
Info: Found entity 1: ramdp
Info: Elaborating entity "ramdp" for hierarchy "ramdp:inst4"
Info: Elaborating entity "altsyncram" for hierarchy "ramdp:inst4|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "ramdp:inst4|altsyncram:altsyncram_component"
Info: Instantiated megafunction "ramdp:inst4|altsyncram:altsyncram_component" with the following parameter:
Info: Parameter "address_reg_b" = "CLOCK1"
Info: Parameter "clock_enable_input_a" = "BYPASS"
Info: Parameter "clock_enable_input_b" = "BYPASS"
Info: Parameter "clock_enable_output_a" = "BYPASS"
Info: Parameter "clock_enable_output_b" = "BYPASS"
Info: Parameter "intended_device_family" = "Cyclone II"
Info: Parameter "lpm_type" = "altsyncram"
Info: Parameter "numwords_a" = "16"
Info: Parameter "numwords_b" = "16"
Info: Parameter "operation_mode" = "DUAL_PORT"
Info: Parameter "outdata_aclr_b" = "NONE"
Info: Parameter "outdata_reg_b" = "CLOCK1"
Info: Parameter "power_up_uninitialized" = "FALSE"
Info: Parameter "ram_block_type" = "M4K"
Info: Parameter "rdcontrol_reg_b" = "CLOCK1"
Info: Parameter "widthad_a" = "4"
Info: Parameter "widthad_b" = "4"
Info: Parameter "width_a" = "8"
Info: Parameter "width_b" = "8"
Info: Parameter "width_byteena_a" = "1"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_puo1.tdf
Info: Found entity 1: altsyncram_puo1
Info: Elaborating entity "altsyncram_puo1" for hierarchy "ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated"
Info: Implemented 84 device resources after synthesis - the final resource count might be different
Info: Implemented 12 input pins
Info: Implemented 10 output pins
Info: Implemented 54 logic cells
Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Peak virtual memory: 190 megabytes
Info: Processing ended: Tue Apr 21 21:27:10 2009
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:03
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