empty_cmp.tan.rpt

基于FPGA编写的VHDL语言

Classic Timing Analyzer report for empty_cmp
Thu Apr 09 15:51:48 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                        ;
+------------------------------+-------+---------------+-------------+------------+-------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From       ; To    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------------+-------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.275 ns   ; wr_addr[3] ; empty ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;            ;       ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------------+-------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------+
; tpd                                                              ;
+-------+-------------------+-----------------+------------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From       ; To    ;
+-------+-------------------+-----------------+------------+-------+
; N/A   ; None              ; 13.275 ns       ; wr_addr[3] ; empty ;
; N/A   ; None              ; 13.209 ns       ; wr_addr[2] ; empty ;
; N/A   ; None              ; 13.103 ns       ; rd_addr[1] ; empty ;
; N/A   ; None              ; 12.981 ns       ; rd_addr[2] ; empty ;
; N/A   ; None              ; 12.903 ns       ; wr_addr[1] ; empty ;
; N/A   ; None              ; 12.526 ns       ; wr_addr[0] ; empty ;
; N/A   ; None              ; 12.493 ns       ; rd_addr[0] ; empty ;
; N/A   ; None              ; 12.302 ns       ; rd_addr[3] ; empty ;
+-------+-------------------+-----------------+------------+-------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Thu Apr 09 15:51:48 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off empty_cmp -c empty_cmp --timing_analysis_only
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Longest tpd from source pin "wr_addr[3]" to destination pin "empty" is 13.275 ns
    Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_44; Fanout = 1; PIN Node = 'wr_addr[3]'
    Info: 2: + IC(6.270 ns) + CELL(0.614 ns) = 7.879 ns; Loc. = LCCOMB_X8_Y1_N0; Fanout = 1; COMB Node = 'Equal0~21'
    Info: 3: + IC(0.357 ns) + CELL(0.206 ns) = 8.442 ns; Loc. = LCCOMB_X8_Y1_N28; Fanout = 1; COMB Node = 'Equal0~23'
    Info: 4: + IC(1.727 ns) + CELL(3.106 ns) = 13.275 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'empty'
    Info: Total cell delay = 4.921 ns ( 37.07 % )
    Info: Total interconnect delay = 8.354 ns ( 62.93 % )
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 129 megabytes
    Info: Processing ended: Thu Apr 09 15:51:49 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01