gray.vhd

基于FPGA编写的VHDL语言

--gray.vhd
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity gray is
generic(n:integer:=5);
port(
    --
    clk:in std_logic;
    --
    en:in std_logic;
    --
    q:out std_logic_vector(n-1 downto 0)
     );
end gray;     

architecture behavioral of gray is
signal reg_q :std_logic_vector(n-1 downto 0);
signal new_q :std_logic_vector(n-1 downto 0);
begin

process(clk,en)
 begin
 if falling_edge(clk) then
    if en ='0' then
    null;
    else
    new_q<=reg_q;
    end if;
    end if;
 end process;
 
 q<=new_q;
 process(new_q)
     variable normal:std_logic_vector(n-1 downto 0);
     variable tem_q:std_logic_vector(n-1 downto 0);  
     begin
     tem_q :=new_q;
     normal(n-1):=tem_q(n-1);
     for i in n-2 downto 0 loop
        normal(i) :=tem_q(i) xor normal(i+1);
       end loop;
     for i in 0 to n-1 loop
            if(normal(i)='0' or i=n-1) then
            tem_q(i) :=not(tem_q(i));
            exit;
           end if;
         end  loop;
      reg_q<=tem_q;
    end process;
  end behavioral;