prev_cmp_sync.map.qmsg

基于FPGA编写的VHDL语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 09 15:30:53 2009 " "Info: Processing started: Thu Apr 09 15:30:53 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sync -c sync " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sync -c sync" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sync.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sync.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sync-behave " "Info: Found design unit 1: sync-behave" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sync " "Info: Found entity 1: sync" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sync " "Info: Elaborating entity \"sync\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addr_a sync.vhd(25) " "Warning (10492): VHDL Process Statement warning at sync.vhd(25): signal \"addr_a\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Error" "EVRFX_VDB_2011_UNCONVERTED" "addr_s\[0\] sync.vhd(26) " "Error (10818): Can't infer register for \"addr_s\[0\]\" at sync.vhd(26) because it does not hold its value outside the clock edge" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 0 0 } }  } 0 10818 "Can't infer register for \"%1!s!\" at %2!s! because it does not hold its value outside the clock edge" 0 0 "" 0 0}
{ "Error" "EVRFX_VDB_2011_UNCONVERTED" "addr_s\[1\] sync.vhd(26) " "Error (10818): Can't infer register for \"addr_s\[1\]\" at sync.vhd(26) because it does not hold its value outside the clock edge" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 0 0 } }  } 0 10818 "Can't infer register for \"%1!s!\" at %2!s! because it does not hold its value outside the clock edge" 0 0 "" 0 0}
{ "Error" "EVRFX_VDB_2011_UNCONVERTED" "addr_s\[2\] sync.vhd(26) " "Error (10818): Can't infer register for \"addr_s\[2\]\" at sync.vhd(26) because it does not hold its value outside the clock edge" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 0 0 } }  } 0 10818 "Can't infer register for \"%1!s!\" at %2!s! because it does not hold its value outside the clock edge" 0 0 "" 0 0}
{ "Error" "EVRFX_VDB_2011_UNCONVERTED" "addr_s\[3\] sync.vhd(26) " "Error (10818): Can't infer register for \"addr_s\[3\]\" at sync.vhd(26) because it does not hold its value outside the clock edge" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 0 0 } }  } 0 10818 "Can't infer register for \"%1!s!\" at %2!s! because it does not hold its value outside the clock edge" 0 0 "" 0 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "sync.vhd(26) " "Error (10822): HDL error at sync.vhd(26): couldn't implement registers for assignments on this clock edge" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 6 s 1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 6 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "178 " "Error: Peak virtual memory: 178 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Apr 09 15:30:55 2009 " "Error: Processing ended: Thu Apr 09 15:30:55 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}