prev_cmp_sync.tan.qmsg

基于FPGA编写的VHDL语言

{ "Info" "ITDB_TH_RESULT" "temp\[1\] addr_a\[1\] clk -3.845 ns register " "Info: th for register \"temp\[1\]\" (data pin = \"addr_a\[1\]\", clock pin = \"clk\") is -3.845 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.868 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.666 ns) 2.868 ns temp\[1\] 3 REG LCFF_X1_Y1_N27 1 " "Info: 3: + IC(0.923 ns) + CELL(0.666 ns) = 2.868 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'temp\[1\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk~clkctrl temp[1] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.97 % ) " "Info: Total cell delay = 1.806 ns ( 62.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.062 ns ( 37.03 % ) " "Info: Total interconnect delay = 1.062 ns ( 37.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl temp[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} temp[1] {} } { 0.000ns 0.000ns 0.139ns 0.923ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.019 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.019 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns addr_a\[1\] 1 PIN PIN_58 1 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_58; Fanout = 1; PIN Node = 'addr_a\[1\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr_a[1] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.701 ns) + CELL(0.206 ns) 6.911 ns temp\[1\]~feeder 2 COMB LCCOMB_X1_Y1_N26 1 " "Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.911 ns; Loc. = LCCOMB_X1_Y1_N26; Fanout = 1; COMB Node = 'temp\[1\]~feeder'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.907 ns" { addr_a[1] temp[1]~feeder } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.019 ns temp\[1\] 3 REG LCFF_X1_Y1_N27 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.019 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'temp\[1\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { temp[1]~feeder temp[1] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.318 ns ( 18.78 % ) " "Info: Total cell delay = 1.318 ns ( 18.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.701 ns ( 81.22 % ) " "Info: Total interconnect delay = 5.701 ns ( 81.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.019 ns" { addr_a[1] temp[1]~feeder temp[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.019 ns" { addr_a[1] {} addr_a[1]~combout {} temp[1]~feeder {} temp[1] {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 1.004ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl temp[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} temp[1] {} } { 0.000ns 0.000ns 0.139ns 0.923ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.019 ns" { addr_a[1] temp[1]~feeder temp[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.019 ns" { addr_a[1] {} addr_a[1]~combout {} temp[1]~feeder {} temp[1] {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 1.004ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "131 " "Info: Peak virtual memory: 131 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 09 15:28:56 2009 " "Info: Processing ended: Thu Apr 09 15:28:56 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}