prev_cmp_sync.tan.qmsg

基于FPGA编写的VHDL语言

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } } { "d:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register temp\[1\] addr_s\[1\]~reg0 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"temp\[1\]\" and destination register \"addr_s\[1\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.739 ns + Longest register register " "Info: + Longest register to register delay is 0.739 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[1\] 1 REG LCFF_X1_Y1_N27 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'temp\[1\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp[1] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.206 ns) 0.631 ns addr_s\[1\]~reg0feeder 2 COMB LCCOMB_X1_Y1_N0 1 " "Info: 2: + IC(0.425 ns) + CELL(0.206 ns) = 0.631 ns; Loc. = LCCOMB_X1_Y1_N0; Fanout = 1; COMB Node = 'addr_s\[1\]~reg0feeder'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.631 ns" { temp[1] addr_s[1]~reg0feeder } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.739 ns addr_s\[1\]~reg0 3 REG LCFF_X1_Y1_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.739 ns; Loc. = LCFF_X1_Y1_N1; Fanout = 1; REG Node = 'addr_s\[1\]~reg0'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { addr_s[1]~reg0feeder addr_s[1]~reg0 } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 42.49 % ) " "Info: Total cell delay = 0.314 ns ( 42.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.425 ns ( 57.51 % ) " "Info: Total interconnect delay = 0.425 ns ( 57.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.739 ns" { temp[1] addr_s[1]~reg0feeder addr_s[1]~reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.739 ns" { temp[1] {} addr_s[1]~reg0feeder {} addr_s[1]~reg0 {} } { 0.000ns 0.425ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.868 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.666 ns) 2.868 ns addr_s\[1\]~reg0 3 REG LCFF_X1_Y1_N1 1 " "Info: 3: + IC(0.923 ns) + CELL(0.666 ns) = 2.868 ns; Loc. = LCFF_X1_Y1_N1; Fanout = 1; REG Node = 'addr_s\[1\]~reg0'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk~clkctrl addr_s[1]~reg0 } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.97 % ) " "Info: Total cell delay = 1.806 ns ( 62.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.062 ns ( 37.03 % ) " "Info: Total interconnect delay = 1.062 ns ( 37.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl addr_s[1]~reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} addr_s[1]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.923ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.868 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.666 ns) 2.868 ns temp\[1\] 3 REG LCFF_X1_Y1_N27 1 " "Info: 3: + IC(0.923 ns) + CELL(0.666 ns) = 2.868 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'temp\[1\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk~clkctrl temp[1] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.97 % ) " "Info: Total cell delay = 1.806 ns ( 62.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.062 ns ( 37.03 % ) " "Info: Total interconnect delay = 1.062 ns ( 37.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl temp[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} temp[1] {} } { 0.000ns 0.000ns 0.139ns 0.923ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl addr_s[1]~reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} addr_s[1]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.923ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl temp[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} temp[1] {} } { 0.000ns 0.000ns 0.139ns 0.923ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.739 ns" { temp[1] addr_s[1]~reg0feeder addr_s[1]~reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.739 ns" { temp[1] {} addr_s[1]~reg0feeder {} addr_s[1]~reg0 {} } { 0.000ns 0.425ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl addr_s[1]~reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} addr_s[1]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.923ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl temp[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} temp[1] {} } { 0.000ns 0.000ns 0.139ns 0.923ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr_s[1]~reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { addr_s[1]~reg0 {} } {  } {  } "" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "temp\[2\] addr_a\[2\] clk 5.070 ns register " "Info: tsu for register \"temp\[2\]\" (data pin = \"addr_a\[2\]\", clock pin = \"clk\") is 5.070 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.964 ns + Longest pin register " "Info: + Longest pin to register delay is 7.964 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns addr_a\[2\] 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'addr_a\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr_a[2] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.540 ns) + CELL(0.460 ns) 7.964 ns temp\[2\] 2 REG LCFF_X30_Y7_N27 1 " "Info: 2: + IC(6.540 ns) + CELL(0.460 ns) = 7.964 ns; Loc. = LCFF_X30_Y7_N27; Fanout = 1; REG Node = 'temp\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { addr_a[2] temp[2] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.424 ns ( 17.88 % ) " "Info: Total cell delay = 1.424 ns ( 17.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.540 ns ( 82.12 % ) " "Info: Total interconnect delay = 6.540 ns ( 82.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.964 ns" { addr_a[2] temp[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.964 ns" { addr_a[2] {} addr_a[2]~combout {} temp[2] {} } { 0.000ns 0.000ns 6.540ns } { 0.000ns 0.964ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.854 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.854 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.909 ns) + CELL(0.666 ns) 2.854 ns temp\[2\] 3 REG LCFF_X30_Y7_N27 1 " "Info: 3: + IC(0.909 ns) + CELL(0.666 ns) = 2.854 ns; Loc. = LCFF_X30_Y7_N27; Fanout = 1; REG Node = 'temp\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.575 ns" { clk~clkctrl temp[2] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.28 % ) " "Info: Total cell delay = 1.806 ns ( 63.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.048 ns ( 36.72 % ) " "Info: Total interconnect delay = 1.048 ns ( 36.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.854 ns" { clk clk~clkctrl temp[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.854 ns" { clk {} clk~combout {} clk~clkctrl {} temp[2] {} } { 0.000ns 0.000ns 0.139ns 0.909ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.964 ns" { addr_a[2] temp[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.964 ns" { addr_a[2] {} addr_a[2]~combout {} temp[2] {} } { 0.000ns 0.000ns 6.540ns } { 0.000ns 0.964ns 0.460ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.854 ns" { clk clk~clkctrl temp[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.854 ns" { clk {} clk~combout {} clk~clkctrl {} temp[2] {} } { 0.000ns 0.000ns 0.139ns 0.909ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk addr_s\[0\] addr_s\[0\]~reg0 7.467 ns register " "Info: tco from clock \"clk\" to destination pin \"addr_s\[0\]\" through register \"addr_s\[0\]~reg0\" is 7.467 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.878 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.933 ns) + CELL(0.666 ns) 2.878 ns addr_s\[0\]~reg0 3 REG LCFF_X14_Y4_N9 1 " "Info: 3: + IC(0.933 ns) + CELL(0.666 ns) = 2.878 ns; Loc. = LCFF_X14_Y4_N9; Fanout = 1; REG Node = 'addr_s\[0\]~reg0'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.599 ns" { clk~clkctrl addr_s[0]~reg0 } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.75 % ) " "Info: Total cell delay = 1.806 ns ( 62.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.072 ns ( 37.25 % ) " "Info: Total interconnect delay = 1.072 ns ( 37.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.878 ns" { clk clk~clkctrl addr_s[0]~reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.878 ns" { clk {} clk~combout {} clk~clkctrl {} addr_s[0]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.933ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.285 ns + Longest register pin " "Info: + Longest register to pin delay is 4.285 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addr_s\[0\]~reg0 1 REG LCFF_X14_Y4_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y4_N9; Fanout = 1; REG Node = 'addr_s\[0\]~reg0'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr_s[0]~reg0 } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(3.286 ns) 4.285 ns addr_s\[0\] 2 PIN PIN_69 0 " "Info: 2: + IC(0.999 ns) + CELL(3.286 ns) = 4.285 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'addr_s\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.285 ns" { addr_s[0]~reg0 addr_s[0] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.286 ns ( 76.69 % ) " "Info: Total cell delay = 3.286 ns ( 76.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 23.31 % ) " "Info: Total interconnect delay = 0.999 ns ( 23.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.285 ns" { addr_s[0]~reg0 addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.285 ns" { addr_s[0]~reg0 {} addr_s[0] {} } { 0.000ns 0.999ns } { 0.000ns 3.286ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.878 ns" { clk clk~clkctrl addr_s[0]~reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.878 ns" { clk {} clk~combout {} clk~clkctrl {} addr_s[0]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.933ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.285 ns" { addr_s[0]~reg0 addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.285 ns" { addr_s[0]~reg0 {} addr_s[0] {} } { 0.000ns 0.999ns } { 0.000ns 3.286ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}