prev_cmp_full_empty.map.qmsg

基于FPGA编写的VHDL语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 10 20:22:15 2009 " "Info: Processing started: Fri Apr 10 20:22:15 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off full_empty -c full_empty " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off full_empty -c full_empty" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "full_empty.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file full_empty.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_empty " "Info: Found entity 1: full_empty" {  } { { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "full_empty " "Info: Elaborating entity \"full_empty\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Error" "EGDFX_WIDTH_MISMATCH_FOR_PORT" "addr_a\[n-1..0\] sync inst \"rd_addr_grey\[4..0\]\" " "Error: Width mismatch in port \"addr_a\[n-1..0\]\" of instance \"inst\" and type sync -- source is \"\"rd_addr_grey\[4..0\]\"\"" {  } { { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 280 144 184 280 "" "" } { 280 144 144 536 "" "" } { 536 144 192 536 "" "" } { 536 104 144 536 "" "" } { 528 -72 104 544 "rd_addr_grey\[4..0\]" "" } { 232 184 376 328 "inst" "" } } } }  } 0 0 "Width mismatch in port \"%1!s!\" of instance \"%3!s!\" and type %2!s! -- source is \"%4!s!\"" 0 0 "" 0 0}
{ "Error" "EGDFX_WIDTH_MISMATCH_FOR_PORT" "grey\[n-1..0\] g2b inst3 \"wr_addr_gery\[4..0\]\" " "Error: Width mismatch in port \"grey\[n-1..0\]\" of instance \"inst3\" and type g2b -- source is \"\"wr_addr_gery\[4..0\]\"\"" {  } { { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 424 160 176 424 "" "" } { 104 160 160 424 "" "" } { 104 160 176 104 "" "" } { 104 152 160 104 "" "" } { 96 -32 152 112 "wr_addr_gery\[4..0\]" "" } { 72 176 344 168 "inst3" "" } } } }  } 0 0 "Width mismatch in port \"%1!s!\" of instance \"%3!s!\" and type %2!s! -- source is \"%4!s!\"" 0 0 "" 0 0}
{ "Error" "EGDFX_WIDTH_MISMATCH_FOR_PORT" "addr_a\[n-1..0\] sync inst7 \"wr_addr_gery\[4..0\]\" " "Error: Width mismatch in port \"addr_a\[n-1..0\]\" of instance \"inst7\" and type sync -- source is \"\"wr_addr_gery\[4..0\]\"\"" {  } { { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 424 160 176 424 "" "" } { 104 160 160 424 "" "" } { 104 160 176 104 "" "" } { 104 152 160 104 "" "" } { 96 -32 152 112 "wr_addr_gery\[4..0\]" "" } { 376 176 368 472 "inst7" "" } } } }  } 0 0 "Width mismatch in port \"%1!s!\" of instance \"%3!s!\" and type %2!s! -- source is \"%4!s!\"" 0 0 "" 0 0}
{ "Error" "EGDFX_WIDTH_MISMATCH_FOR_PORT" "grey\[n-1..0\] g2b inst9 \"rd_addr_grey\[4..0\]\" " "Error: Width mismatch in port \"grey\[n-1..0\]\" of instance \"inst9\" and type g2b -- source is \"\"rd_addr_grey\[4..0\]\"\"" {  } { { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 280 144 184 280 "" "" } { 280 144 144 536 "" "" } { 536 144 192 536 "" "" } { 536 104 144 536 "" "" } { 528 -72 104 544 "rd_addr_grey\[4..0\]" "" } { 504 192 360 600 "inst9" "" } } } }  } 0 0 "Width mismatch in port \"%1!s!\" of instance \"%3!s!\" and type %2!s! -- source is \"%4!s!\"" 0 0 "" 0 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 5 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Error: Peak virtual memory: 163 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Apr 10 20:22:16 2009 " "Error: Processing ended: Fri Apr 10 20:22:16 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}