fifotop.hif

基于FPGA编写的VHDL语言

Version 8.1 Build 163 10/28/2008 SJ Full Version
11
945
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
full_empty
# storage
db|fifotop.(1).cnf
db|fifotop.(1).cnf
# case_insensitive
# source_file
full_empty.bdf
f451bb894f5bdd52146d19ee3692ec98
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
full_empty:inst3
}
# macro_sequence

# end
# entity
empty_cmp
# storage
db|fifotop.(2).cnf
db|fifotop.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
empty_cmp.vhd
5ca244f5d5d0aadbef367b2ccd5c71da
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
n
5
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
full_empty:inst3|empty_cmp:inst5
}
# lmf
d:|altera|81|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
g2b
# storage
db|fifotop.(3).cnf
db|fifotop.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
g2b.vhd
c65b81cf96064d51322f9fdd3fa842
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
n
5
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
full_empty:inst3|g2b:inst9
full_empty:inst3|g2b:inst8
full_empty:inst3|g2b:inst6
full_empty:inst3|g2b:inst3
g2b:inst1
g2b:inst2
}
# lmf
d:|altera|81|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sync
# storage
db|fifotop.(4).cnf
db|fifotop.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sync.vhd
c587a7276be5943c6f7047d6e347c
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
n
5
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
full_empty:inst3|sync:inst7
full_empty:inst3|sync:inst
}
# lmf
d:|altera|81|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
full_cmp
# storage
db|fifotop.(5).cnf
db|fifotop.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
full_cmp.vhd
90a7e47c3d40253020d4ec4e8554e52
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
n
5
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
full_empty:inst3|full_cmp:inst4
}
# lmf
d:|altera|81|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
gray
# storage
db|fifotop.(6).cnf
db|fifotop.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
gray.vhd
96c8a6c7337d66f832fd132da605b
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
n
5
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
gray:inst6
gray:inst
}
# lmf
d:|altera|81|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
ramdp
# storage
db|fifotop.(7).cnf
db|fifotop.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
ramdp.vhd
7fa65f3e6ed859198b3a64f1e5ffa60
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
ramdp:inst4
}
# lmf
d:|altera|81|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
altsyncram
# storage
db|fifotop.(8).cnf
db|fifotop.(8).cnf
# case_insensitive
# source_file
d:|altera|81|quartus|libraries|megafunctions|altsyncram.tdf
428afb9bbf965842aa82c9b05526af
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
4
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
16
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
4
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
16
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_puo1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
d:|altera|81|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
d:|altera|81|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
d:|altera|81|quartus|libraries|megafunctions|aglobal81.inc
ba79644cade9dcbd5df4af72a9b02986
d:|altera|81|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
d:|altera|81|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|altera|81|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
d:|altera|81|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
d:|altera|81|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
d:|altera|81|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
ramdp:inst4|altsyncram:altsyncram_component
}
# macro_sequence

# end
# entity
altsyncram_puo1
# storage
db|fifotop.(9).cnf
db|fifotop.(9).cnf
# case_insensitive
# source_file
db|altsyncram_puo1.tdf
41e955ff4a8a5e0ab1ce6ab2017de6
7
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated
}
# macro_sequence

# end
# entity
fifotop
# storage
db|fifotop.(0).cnf
db|fifotop.(0).cnf
# case_insensitive
# source_file
fifotop.bdf
f3f3f9e8df75f38ae8a14e9a0ec2d9
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence

# end
# complete