empty_cmp.tan.qmsg

基于FPGA编写的VHDL语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 09 15:51:48 2009 " "Info: Processing started: Thu Apr 09 15:51:48 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off empty_cmp -c empty_cmp --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off empty_cmp -c empty_cmp --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "wr_addr\[3\] empty 13.275 ns Longest " "Info: Longest tpd from source pin \"wr_addr\[3\]\" to destination pin \"empty\" is 13.275 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns wr_addr\[3\] 1 PIN PIN_44 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_44; Fanout = 1; PIN Node = 'wr_addr\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_addr[3] } "NODE_NAME" } } { "empty_cmp.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/empty_cmp.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.270 ns) + CELL(0.614 ns) 7.879 ns Equal0~21 2 COMB LCCOMB_X8_Y1_N0 1 " "Info: 2: + IC(6.270 ns) + CELL(0.614 ns) = 7.879 ns; Loc. = LCCOMB_X8_Y1_N0; Fanout = 1; COMB Node = 'Equal0~21'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.884 ns" { wr_addr[3] Equal0~21 } "NODE_NAME" } } { "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.206 ns) 8.442 ns Equal0~23 3 COMB LCCOMB_X8_Y1_N28 1 " "Info: 3: + IC(0.357 ns) + CELL(0.206 ns) = 8.442 ns; Loc. = LCCOMB_X8_Y1_N28; Fanout = 1; COMB Node = 'Equal0~23'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.563 ns" { Equal0~21 Equal0~23 } "NODE_NAME" } } { "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.727 ns) + CELL(3.106 ns) 13.275 ns empty 4 PIN PIN_45 0 " "Info: 4: + IC(1.727 ns) + CELL(3.106 ns) = 13.275 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'empty'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.833 ns" { Equal0~23 empty } "NODE_NAME" } } { "empty_cmp.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/empty_cmp.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.921 ns ( 37.07 % ) " "Info: Total cell delay = 4.921 ns ( 37.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.354 ns ( 62.93 % ) " "Info: Total interconnect delay = 8.354 ns ( 62.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "13.275 ns" { wr_addr[3] Equal0~21 Equal0~23 empty } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "13.275 ns" { wr_addr[3] {} wr_addr[3]~combout {} Equal0~21 {} Equal0~23 {} empty {} } { 0.000ns 0.000ns 6.270ns 0.357ns 1.727ns } { 0.000ns 0.995ns 0.614ns 0.206ns 3.106ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "129 " "Info: Peak virtual memory: 129 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 09 15:51:49 2009 " "Info: Processing ended: Thu Apr 09 15:51:49 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}