fifotop.tan.qmsg

基于FPGA编写的VHDL语言

{ "Info" "ITDB_FULL_TCO_RESULT" "wr_clk full gray:inst\|new_q\[4\] 12.031 ns register " "Info: tco from clock \"wr_clk\" to destination pin \"full\" through register \"gray:inst\|new_q\[4\]\" is 12.031 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr_clk source 2.822 ns + Longest register " "Info: + Longest clock path from clock \"wr_clk\" to source register is 2.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns wr_clk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'wr_clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_clk } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 120 -32 136 136 "wr_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns wr_clk~clkctrl 2 COMB CLKCTRL_G1 36 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 36; COMB Node = 'wr_clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { wr_clk wr_clk~clkctrl } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 120 -32 136 136 "wr_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 2.822 ns gray:inst\|new_q\[4\] 3 REG LCFF_X13_Y9_N23 9 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 2.822 ns; Loc. = LCFF_X13_Y9_N23; Fanout = 9; REG Node = 'gray:inst\|new_q\[4\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { wr_clk~clkctrl gray:inst|new_q[4] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.796 ns ( 63.64 % ) " "Info: Total cell delay = 1.796 ns ( 63.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 36.36 % ) " "Info: Total interconnect delay = 1.026 ns ( 36.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.822 ns" { wr_clk wr_clk~clkctrl gray:inst|new_q[4] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.822 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} gray:inst|new_q[4] {} } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.905 ns + Longest register pin " "Info: + Longest register to pin delay is 8.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gray:inst\|new_q\[4\] 1 REG LCFF_X13_Y9_N23 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y9_N23; Fanout = 9; REG Node = 'gray:inst\|new_q\[4\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { gray:inst|new_q[4] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.786 ns) + CELL(0.623 ns) 1.409 ns full_empty:inst3\|g2b:inst3\|norm\[2\] 2 COMB LCCOMB_X12_Y9_N24 4 " "Info: 2: + IC(0.786 ns) + CELL(0.623 ns) = 1.409 ns; Loc. = LCCOMB_X12_Y9_N24; Fanout = 4; COMB Node = 'full_empty:inst3\|g2b:inst3\|norm\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.409 ns" { gray:inst|new_q[4] full_empty:inst3|g2b:inst3|norm[2] } "NODE_NAME" } } { "g2b.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/g2b.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.370 ns) 2.818 ns full_empty:inst3\|full_cmp:inst4\|full 3 COMB LCCOMB_X13_Y9_N30 2 " "Info: 3: + IC(1.039 ns) + CELL(0.370 ns) = 2.818 ns; Loc. = LCCOMB_X13_Y9_N30; Fanout = 2; COMB Node = 'full_empty:inst3\|full_cmp:inst4\|full'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.409 ns" { full_empty:inst3|g2b:inst3|norm[2] full_empty:inst3|full_cmp:inst4|full } "NODE_NAME" } } { "full_cmp.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/full_cmp.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.981 ns) + CELL(3.106 ns) 8.905 ns full 4 PIN PIN_13 0 " "Info: 4: + IC(2.981 ns) + CELL(3.106 ns) = 8.905 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'full'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.087 ns" { full_empty:inst3|full_cmp:inst4|full full } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 392 720 896 408 "full" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.099 ns ( 46.03 % ) " "Info: Total cell delay = 4.099 ns ( 46.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.806 ns ( 53.97 % ) " "Info: Total interconnect delay = 4.806 ns ( 53.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.905 ns" { gray:inst|new_q[4] full_empty:inst3|g2b:inst3|norm[2] full_empty:inst3|full_cmp:inst4|full full } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.905 ns" { gray:inst|new_q[4] {} full_empty:inst3|g2b:inst3|norm[2] {} full_empty:inst3|full_cmp:inst4|full {} full {} } { 0.000ns 0.786ns 1.039ns 2.981ns } { 0.000ns 0.623ns 0.370ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.822 ns" { wr_clk wr_clk~clkctrl gray:inst|new_q[4] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.822 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} gray:inst|new_q[4] {} } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.905 ns" { gray:inst|new_q[4] full_empty:inst3|g2b:inst3|norm[2] full_empty:inst3|full_cmp:inst4|full full } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.905 ns" { gray:inst|new_q[4] {} full_empty:inst3|g2b:inst3|norm[2] {} full_empty:inst3|full_cmp:inst4|full {} full {} } { 0.000ns 0.786ns 1.039ns 2.981ns } { 0.000ns 0.623ns 0.370ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_datain_reg5 data\[5\] wr_clk 0.343 ns memory " "Info: th for memory \"ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_datain_reg5\" (data pin = \"data\[5\]\", clock pin = \"wr_clk\") is 0.343 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr_clk destination 2.909 ns + Longest memory " "Info: + Longest clock path from clock \"wr_clk\" to destination memory is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns wr_clk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'wr_clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_clk } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 120 -32 136 136 "wr_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns wr_clk~clkctrl 2 COMB CLKCTRL_G1 36 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 36; COMB Node = 'wr_clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { wr_clk wr_clk~clkctrl } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 120 -32 136 136 "wr_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.834 ns) 2.909 ns ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_datain_reg5 3 MEM M4K_X11_Y9 1 " "Info: 3: + IC(0.806 ns) + CELL(0.834 ns) = 2.909 ns; Loc. = M4K_X11_Y9; Fanout = 1; MEM Node = 'ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_datain_reg5'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.640 ns" { wr_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 } "NODE_NAME" } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.964 ns ( 67.51 % ) " "Info: Total cell delay = 1.964 ns ( 67.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.945 ns ( 32.49 % ) " "Info: Total interconnect delay = 0.945 ns ( 32.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { wr_clk wr_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.130ns 0.000ns 0.834ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.267 ns + " "Info: + Micro hold delay of destination is 0.267 ns" {  } { { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.833 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 2.833 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns data\[5\] 1 PIN PIN_27 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_27; Fanout = 1; PIN Node = 'data\[5\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[5] } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 208 592 760 224 "data\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.575 ns) + CELL(0.128 ns) 2.833 ns ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_datain_reg5 2 MEM M4K_X11_Y9 1 " "Info: 2: + IC(1.575 ns) + CELL(0.128 ns) = 2.833 ns; Loc. = M4K_X11_Y9; Fanout = 1; MEM Node = 'ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_datain_reg5'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.703 ns" { data[5] ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 } "NODE_NAME" } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.258 ns ( 44.41 % ) " "Info: Total cell delay = 1.258 ns ( 44.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.575 ns ( 55.59 % ) " "Info: Total interconnect delay = 1.575 ns ( 55.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.833 ns" { data[5] ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.833 ns" { data[5] {} data[5]~combout {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 {} } { 0.000ns 0.000ns 1.575ns } { 0.000ns 1.130ns 0.128ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { wr_clk wr_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.130ns 0.000ns 0.834ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.833 ns" { data[5] ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.833 ns" { data[5] {} data[5]~combout {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_datain_reg5 {} } { 0.000ns 0.000ns 1.575ns } { 0.000ns 1.130ns 0.128ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "131 " "Info: Peak virtual memory: 131 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 21 21:27:19 2009 " "Info: Processing ended: Tue Apr 21 21:27:19 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}