fifotop.tan.qmsg

基于FPGA编写的VHDL语言

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "rd_clk " "Info: Assuming node \"rd_clk\" is an undefined clock" {  } { { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 480 -24 144 496 "rd_clk" "" } } } } { "d:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "rd_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wr_clk " "Info: Assuming node \"wr_clk\" is an undefined clock" {  } { { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 120 -32 136 136 "wr_clk" "" } } } } { "d:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "wr_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "rd_clk register gray:inst6\|new_q\[2\] memory ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0 96.02 MHz 10.414 ns Internal " "Info: Clock \"rd_clk\" has Internal fmax of 96.02 MHz between source register \"gray:inst6\|new_q\[2\]\" and destination memory \"ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0\" (period= 10.414 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.972 ns + Longest register memory " "Info: + Longest register to memory delay is 4.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gray:inst6\|new_q\[2\] 1 REG LCFF_X12_Y8_N13 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y8_N13; Fanout = 6; REG Node = 'gray:inst6\|new_q\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { gray:inst6|new_q[2] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.650 ns) 1.148 ns full_empty:inst3\|g2b:inst9\|norm\[1\] 2 COMB LCCOMB_X12_Y8_N2 5 " "Info: 2: + IC(0.498 ns) + CELL(0.650 ns) = 1.148 ns; Loc. = LCCOMB_X12_Y8_N2; Fanout = 5; COMB Node = 'full_empty:inst3\|g2b:inst9\|norm\[1\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.148 ns" { gray:inst6|new_q[2] full_empty:inst3|g2b:inst9|norm[1] } "NODE_NAME" } } { "g2b.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/g2b.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.206 ns) 1.750 ns full_empty:inst3\|empty_cmp:inst5\|Equal0~86 3 COMB LCCOMB_X12_Y8_N20 2 " "Info: 3: + IC(0.396 ns) + CELL(0.206 ns) = 1.750 ns; Loc. = LCCOMB_X12_Y8_N20; Fanout = 2; COMB Node = 'full_empty:inst3\|empty_cmp:inst5\|Equal0~86'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.602 ns" { full_empty:inst3|g2b:inst9|norm[1] full_empty:inst3|empty_cmp:inst5|Equal0~86 } "NODE_NAME" } } { "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.406 ns) + CELL(0.370 ns) 2.526 ns full_empty:inst3\|inst11 4 COMB LCCOMB_X12_Y8_N28 7 " "Info: 4: + IC(0.406 ns) + CELL(0.370 ns) = 2.526 ns; Loc. = LCCOMB_X12_Y8_N28; Fanout = 7; COMB Node = 'full_empty:inst3\|inst11'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.776 ns" { full_empty:inst3|empty_cmp:inst5|Equal0~86 full_empty:inst3|inst11 } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 576 760 824 624 "inst11" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.621 ns) + CELL(0.825 ns) 4.972 ns ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0 5 MEM M4K_X11_Y9 8 " "Info: 5: + IC(1.621 ns) + CELL(0.825 ns) = 4.972 ns; Loc. = M4K_X11_Y9; Fanout = 8; MEM Node = 'ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.446 ns" { full_empty:inst3|inst11 ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.051 ns ( 41.25 % ) " "Info: Total cell delay = 2.051 ns ( 41.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.921 ns ( 58.75 % ) " "Info: Total interconnect delay = 2.921 ns ( 58.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.972 ns" { gray:inst6|new_q[2] full_empty:inst3|g2b:inst9|norm[1] full_empty:inst3|empty_cmp:inst5|Equal0~86 full_empty:inst3|inst11 ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.972 ns" { gray:inst6|new_q[2] {} full_empty:inst3|g2b:inst9|norm[1] {} full_empty:inst3|empty_cmp:inst5|Equal0~86 {} full_empty:inst3|inst11 {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.498ns 0.396ns 0.406ns 1.621ns } { 0.000ns 0.650ns 0.206ns 0.370ns 0.825ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.115 ns - Smallest " "Info: - Smallest clock skew is 0.115 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rd_clk destination 2.963 ns + Shortest memory " "Info: + Shortest clock path from clock \"rd_clk\" to destination memory is 2.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns rd_clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rd_clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd_clk } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 480 -24 144 496 "rd_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns rd_clk~clkctrl 2 COMB CLKCTRL_G2 27 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 27; COMB Node = 'rd_clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rd_clk rd_clk~clkctrl } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 480 -24 144 496 "rd_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.878 ns) 2.963 ns ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X11_Y9 8 " "Info: 3: + IC(0.806 ns) + CELL(0.878 ns) = 2.963 ns; Loc. = M4K_X11_Y9; Fanout = 8; MEM Node = 'ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.684 ns" { rd_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.018 ns ( 68.11 % ) " "Info: Total cell delay = 2.018 ns ( 68.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.945 ns ( 31.89 % ) " "Info: Total interconnect delay = 0.945 ns ( 31.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.963 ns" { rd_clk rd_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.963 ns" { rd_clk {} rd_clk~combout {} rd_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rd_clk source 2.848 ns - Longest register " "Info: - Longest clock path from clock \"rd_clk\" to source register is 2.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns rd_clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rd_clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd_clk } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 480 -24 144 496 "rd_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns rd_clk~clkctrl 2 COMB CLKCTRL_G2 27 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 27; COMB Node = 'rd_clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rd_clk rd_clk~clkctrl } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 480 -24 144 496 "rd_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.903 ns) + CELL(0.666 ns) 2.848 ns gray:inst6\|new_q\[2\] 3 REG LCFF_X12_Y8_N13 6 " "Info: 3: + IC(0.903 ns) + CELL(0.666 ns) = 2.848 ns; Loc. = LCFF_X12_Y8_N13; Fanout = 6; REG Node = 'gray:inst6\|new_q\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.569 ns" { rd_clk~clkctrl gray:inst6|new_q[2] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.41 % ) " "Info: Total cell delay = 1.806 ns ( 63.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.042 ns ( 36.59 % ) " "Info: Total interconnect delay = 1.042 ns ( 36.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.848 ns" { rd_clk rd_clk~clkctrl gray:inst6|new_q[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.848 ns" { rd_clk {} rd_clk~combout {} rd_clk~clkctrl {} gray:inst6|new_q[2] {} } { 0.000ns 0.000ns 0.139ns 0.903ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.963 ns" { rd_clk rd_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.963 ns" { rd_clk {} rd_clk~combout {} rd_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.848 ns" { rd_clk rd_clk~clkctrl gray:inst6|new_q[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.848 ns" { rd_clk {} rd_clk~combout {} rd_clk~clkctrl {} gray:inst6|new_q[2] {} } { 0.000ns 0.000ns 0.139ns 0.903ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.972 ns" { gray:inst6|new_q[2] full_empty:inst3|g2b:inst9|norm[1] full_empty:inst3|empty_cmp:inst5|Equal0~86 full_empty:inst3|inst11 ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.972 ns" { gray:inst6|new_q[2] {} full_empty:inst3|g2b:inst9|norm[1] {} full_empty:inst3|empty_cmp:inst5|Equal0~86 {} full_empty:inst3|inst11 {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.498ns 0.396ns 0.406ns 1.621ns } { 0.000ns 0.650ns 0.206ns 0.370ns 0.825ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.963 ns" { rd_clk rd_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.963 ns" { rd_clk {} rd_clk~combout {} rd_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.848 ns" { rd_clk rd_clk~clkctrl gray:inst6|new_q[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.848 ns" { rd_clk {} rd_clk~combout {} rd_clk~clkctrl {} gray:inst6|new_q[2] {} } { 0.000ns 0.000ns 0.139ns 0.903ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "wr_clk register gray:inst\|new_q\[3\] memory ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_we_reg 104.12 MHz 9.604 ns Internal " "Info: Clock \"wr_clk\" has Internal fmax of 104.12 MHz between source register \"gray:inst\|new_q\[3\]\" and destination memory \"ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_we_reg\" (period= 9.604 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.540 ns + Longest register memory " "Info: + Longest register to memory delay is 4.540 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gray:inst\|new_q\[3\] 1 REG LCFF_X13_Y9_N17 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y9_N17; Fanout = 9; REG Node = 'gray:inst\|new_q\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { gray:inst|new_q[3] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.651 ns) 1.173 ns full_empty:inst3\|full_cmp:inst4\|full~23 2 COMB LCCOMB_X13_Y9_N8 3 " "Info: 2: + IC(0.522 ns) + CELL(0.651 ns) = 1.173 ns; Loc. = LCCOMB_X13_Y9_N8; Fanout = 3; COMB Node = 'full_empty:inst3\|full_cmp:inst4\|full~23'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.173 ns" { gray:inst|new_q[3] full_empty:inst3|full_cmp:inst4|full~23 } "NODE_NAME" } } { "full_cmp.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/full_cmp.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.707 ns) + CELL(0.650 ns) 2.530 ns full_empty:inst3\|inst10 3 COMB LCCOMB_X13_Y9_N0 15 " "Info: 3: + IC(0.707 ns) + CELL(0.650 ns) = 2.530 ns; Loc. = LCCOMB_X13_Y9_N0; Fanout = 15; COMB Node = 'full_empty:inst3\|inst10'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.357 ns" { full_empty:inst3|full_cmp:inst4|full~23 full_empty:inst3|inst10 } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 8 824 888 56 "inst10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.228 ns) + CELL(0.782 ns) 4.540 ns ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_we_reg 4 MEM M4K_X11_Y9 0 " "Info: 4: + IC(1.228 ns) + CELL(0.782 ns) = 4.540 ns; Loc. = M4K_X11_Y9; Fanout = 0; MEM Node = 'ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.010 ns" { full_empty:inst3|inst10 ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.083 ns ( 45.88 % ) " "Info: Total cell delay = 2.083 ns ( 45.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.457 ns ( 54.12 % ) " "Info: Total interconnect delay = 2.457 ns ( 54.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.540 ns" { gray:inst|new_q[3] full_empty:inst3|full_cmp:inst4|full~23 full_empty:inst3|inst10 ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.540 ns" { gray:inst|new_q[3] {} full_empty:inst3|full_cmp:inst4|full~23 {} full_empty:inst3|inst10 {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.522ns 0.707ns 1.228ns } { 0.000ns 0.651ns 0.650ns 0.782ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.088 ns - Smallest " "Info: - Smallest clock skew is 0.088 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr_clk destination 2.910 ns + Shortest memory " "Info: + Shortest clock path from clock \"wr_clk\" to destination memory is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns wr_clk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'wr_clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_clk } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 120 -32 136 136 "wr_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns wr_clk~clkctrl 2 COMB CLKCTRL_G1 36 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 36; COMB Node = 'wr_clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { wr_clk wr_clk~clkctrl } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 120 -32 136 136 "wr_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.835 ns) 2.910 ns ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_we_reg 3 MEM M4K_X11_Y9 0 " "Info: 3: + IC(0.806 ns) + CELL(0.835 ns) = 2.910 ns; Loc. = M4K_X11_Y9; Fanout = 0; MEM Node = 'ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.641 ns" { wr_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.965 ns ( 67.53 % ) " "Info: Total cell delay = 1.965 ns ( 67.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.945 ns ( 32.47 % ) " "Info: Total interconnect delay = 0.945 ns ( 32.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.910 ns" { wr_clk wr_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.910 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.130ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr_clk source 2.822 ns - Longest register " "Info: - Longest clock path from clock \"wr_clk\" to source register is 2.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns wr_clk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'wr_clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_clk } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 120 -32 136 136 "wr_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns wr_clk~clkctrl 2 COMB CLKCTRL_G1 36 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 36; COMB Node = 'wr_clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { wr_clk wr_clk~clkctrl } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 120 -32 136 136 "wr_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 2.822 ns gray:inst\|new_q\[3\] 3 REG LCFF_X13_Y9_N17 9 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 2.822 ns; Loc. = LCFF_X13_Y9_N17; Fanout = 9; REG Node = 'gray:inst\|new_q\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { wr_clk~clkctrl gray:inst|new_q[3] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.796 ns ( 63.64 % ) " "Info: Total cell delay = 1.796 ns ( 63.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 36.36 % ) " "Info: Total interconnect delay = 1.026 ns ( 36.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.822 ns" { wr_clk wr_clk~clkctrl gray:inst|new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.822 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} gray:inst|new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.910 ns" { wr_clk wr_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.910 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.130ns 0.000ns 0.835ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.822 ns" { wr_clk wr_clk~clkctrl gray:inst|new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.822 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} gray:inst|new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.540 ns" { gray:inst|new_q[3] full_empty:inst3|full_cmp:inst4|full~23 full_empty:inst3|inst10 ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.540 ns" { gray:inst|new_q[3] {} full_empty:inst3|full_cmp:inst4|full~23 {} full_empty:inst3|inst10 {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.522ns 0.707ns 1.228ns } { 0.000ns 0.651ns 0.650ns 0.782ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.910 ns" { wr_clk wr_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.910 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.130ns 0.000ns 0.835ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.822 ns" { wr_clk wr_clk~clkctrl gray:inst|new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.822 ns" { wr_clk {} wr_clk~combout {} wr_clk~clkctrl {} gray:inst|new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0 rden rd_clk 7.883 ns memory " "Info: tsu for memory \"ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0\" (data pin = \"rden\", clock pin = \"rd_clk\") is 7.883 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.800 ns + Longest pin memory " "Info: + Longest pin to memory delay is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns rden 1 PIN PIN_47 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_47; Fanout = 1; PIN Node = 'rden'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rden } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 360 -24 144 376 "rden" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.708 ns) + CELL(0.651 ns) 8.354 ns full_empty:inst3\|inst11 2 COMB LCCOMB_X12_Y8_N28 7 " "Info: 2: + IC(6.708 ns) + CELL(0.651 ns) = 8.354 ns; Loc. = LCCOMB_X12_Y8_N28; Fanout = 7; COMB Node = 'full_empty:inst3\|inst11'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.359 ns" { rden full_empty:inst3|inst11 } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 576 760 824 624 "inst11" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.621 ns) + CELL(0.825 ns) 10.800 ns ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X11_Y9 8 " "Info: 3: + IC(1.621 ns) + CELL(0.825 ns) = 10.800 ns; Loc. = M4K_X11_Y9; Fanout = 8; MEM Node = 'ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.446 ns" { full_empty:inst3|inst11 ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.471 ns ( 22.88 % ) " "Info: Total cell delay = 2.471 ns ( 22.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.329 ns ( 77.12 % ) " "Info: Total interconnect delay = 8.329 ns ( 77.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { rden full_empty:inst3|inst11 ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { rden {} rden~combout {} full_empty:inst3|inst11 {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 6.708ns 1.621ns } { 0.000ns 0.995ns 0.651ns 0.825ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rd_clk destination 2.963 ns - Shortest memory " "Info: - Shortest clock path from clock \"rd_clk\" to destination memory is 2.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns rd_clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rd_clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd_clk } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 480 -24 144 496 "rd_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns rd_clk~clkctrl 2 COMB CLKCTRL_G2 27 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 27; COMB Node = 'rd_clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rd_clk rd_clk~clkctrl } "NODE_NAME" } } { "fifotop.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/fifotop.bdf" { { 480 -24 144 496 "rd_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.878 ns) 2.963 ns ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X11_Y9 8 " "Info: 3: + IC(0.806 ns) + CELL(0.878 ns) = 2.963 ns; Loc. = M4K_X11_Y9; Fanout = 8; MEM Node = 'ramdp:inst4\|altsyncram:altsyncram_component\|altsyncram_puo1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.684 ns" { rd_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_puo1.tdf" "" { Text "E:/workroom2/quartusIIex/fifotop/db/altsyncram_puo1.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.018 ns ( 68.11 % ) " "Info: Total cell delay = 2.018 ns ( 68.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.945 ns ( 31.89 % ) " "Info: Total interconnect delay = 0.945 ns ( 31.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.963 ns" { rd_clk rd_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.963 ns" { rd_clk {} rd_clk~combout {} rd_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { rden full_empty:inst3|inst11 ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { rden {} rden~combout {} full_empty:inst3|inst11 {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 6.708ns 1.621ns } { 0.000ns 0.995ns 0.651ns 0.825ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.963 ns" { rd_clk rd_clk~clkctrl ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.963 ns" { rd_clk {} rd_clk~combout {} rd_clk~clkctrl {} ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.806ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}