full_empty.map.qmsg

来自「基于FPGA编写的VHDL语言」· QMSG 代码 · 共 16 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 10 20:23:24 2009 " "Info: Processing started: Fri Apr 10 20:23:24 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off full_empty -c full_empty " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off full_empty -c full_empty" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "full_empty.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file full_empty.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_empty " "Info: Found entity 1: full_empty" {  } { { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "full_empty " "Info: Elaborating entity \"full_empty\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "empty_cmp.vhd 2 1 " "Warning: Using design file empty_cmp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 empty_cmp-behave " "Info: Found design unit 1: empty_cmp-behave" {  } { { "empty_cmp.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/empty_cmp.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 empty_cmp " "Info: Found entity 1: empty_cmp" {  } { { "empty_cmp.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/empty_cmp.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "empty_cmp empty_cmp:inst5 " "Info: Elaborating entity \"empty_cmp\" for hierarchy \"empty_cmp:inst5\"" {  } { { "full_empty.bdf" "inst5" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 488 472 632 584 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "g2b.vhd 2 1 " "Warning: Using design file g2b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 g2b-behave " "Info: Found design unit 1: g2b-behave" {  } { { "g2b.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/g2b.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 g2b " "Info: Found entity 1: g2b" {  } { { "g2b.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/g2b.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "g2b g2b:inst9 " "Info: Elaborating entity \"g2b\" for hierarchy \"g2b:inst9\"" {  } { { "full_empty.bdf" "inst9" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 504 192 360 600 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sync.vhd 2 1 " "Warning: Using design file sync.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sync-behave " "Info: Found design unit 1: sync-behave" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sync " "Info: Found entity 1: sync" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sync sync:inst7 " "Info: Elaborating entity \"sync\" for hierarchy \"sync:inst7\"" {  } { { "full_empty.bdf" "inst7" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 376 176 368 472 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "full_cmp.vhd 2 1 " "Warning: Using design file full_cmp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 full_cmp-behave " "Info: Found design unit 1: full_cmp-behave" {  } { { "full_cmp.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/full_cmp.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 full_cmp " "Info: Found entity 1: full_cmp" {  } { { "full_cmp.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/full_cmp.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_cmp full_cmp:inst4 " "Info: Elaborating entity \"full_cmp\" for hierarchy \"full_cmp:inst4\"" {  } { { "full_empty.bdf" "inst4" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 72 456 600 168 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Info: Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "14 " "Info: Implemented 14 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "31 " "Info: Implemented 31 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "179 " "Info: Peak virtual memory: 179 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 10 20:23:26 2009 " "Info: Processing ended: Fri Apr 10 20:23:26 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}