fifotop.hier_info

来自「基于FPGA编写的VHDL语言」· HIER_INFO 代码 · 共 471 行 · 第 1/2 页

|fifotop
full <= full_empty:inst3.full
wren => full_empty:inst3.wren
wr_clk => full_empty:inst3.wrclk
wr_clk => gray:inst.clk
wr_clk => ramdp:inst4.wrclock
rd_clk => full_empty:inst3.rdclk
rd_clk => gray:inst6.clk
rd_clk => ramdp:inst4.rdclock
rden => full_empty:inst3.rden
empty <= full_empty:inst3.empty
q[0] <= ramdp:inst4.q[0]
q[1] <= ramdp:inst4.q[1]
q[2] <= ramdp:inst4.q[2]
q[3] <= ramdp:inst4.q[3]
q[4] <= ramdp:inst4.q[4]
q[5] <= ramdp:inst4.q[5]
q[6] <= ramdp:inst4.q[6]
q[7] <= ramdp:inst4.q[7]
data[0] => ramdp:inst4.data[0]
data[1] => ramdp:inst4.data[1]
data[2] => ramdp:inst4.data[2]
data[3] => ramdp:inst4.data[3]
data[4] => ramdp:inst4.data[4]
data[5] => ramdp:inst4.data[5]
data[6] => ramdp:inst4.data[6]
data[7] => ramdp:inst4.data[7]


|fifotop|full_empty:inst3
rden_vaild <= inst11.DB_MAX_OUTPUT_PORT_TYPE
rd_addr_grey[0] => g2b:inst9.grey[0]
rd_addr_grey[0] => sync:inst.addr_a[0]
rd_addr_grey[1] => g2b:inst9.grey[1]
rd_addr_grey[1] => sync:inst.addr_a[1]
rd_addr_grey[2] => g2b:inst9.grey[2]
rd_addr_grey[2] => sync:inst.addr_a[2]
rd_addr_grey[3] => g2b:inst9.grey[3]
rd_addr_grey[3] => sync:inst.addr_a[3]
rd_addr_grey[4] => g2b:inst9.grey[4]
rd_addr_grey[4] => sync:inst.addr_a[4]
rdclk => sync:inst7.clk
wr_addr_gery[0] => sync:inst7.addr_a[0]
wr_addr_gery[0] => g2b:inst3.grey[0]
wr_addr_gery[1] => sync:inst7.addr_a[1]
wr_addr_gery[1] => g2b:inst3.grey[1]
wr_addr_gery[2] => sync:inst7.addr_a[2]
wr_addr_gery[2] => g2b:inst3.grey[2]
wr_addr_gery[3] => sync:inst7.addr_a[3]
wr_addr_gery[3] => g2b:inst3.grey[3]
wr_addr_gery[4] => sync:inst7.addr_a[4]
wr_addr_gery[4] => g2b:inst3.grey[4]
rden => inst11.IN1
empty <= empty_cmp:inst5.empty
full <= full_cmp:inst4.full
wrclk => sync:inst.clk
wren_valid <= inst10.DB_MAX_OUTPUT_PORT_TYPE
wren => inst10.IN0


|fifotop|full_empty:inst3|empty_cmp:inst5
wr_addr[0] => Equal0.IN4
wr_addr[1] => Equal0.IN3
wr_addr[2] => Equal0.IN2
wr_addr[3] => Equal0.IN1
wr_addr[4] => Equal0.IN0
rd_addr[0] => Equal0.IN9
rd_addr[1] => Equal0.IN8
rd_addr[2] => Equal0.IN7
rd_addr[3] => Equal0.IN6
rd_addr[4] => Equal0.IN5
empty <= Equal0.DB_MAX_OUTPUT_PORT_TYPE


|fifotop|full_empty:inst3|g2b:inst9
grey[0] => normal~3.IN0
grey[1] => normal~2.IN0
grey[2] => normal~1.IN0
grey[3] => normal~0.IN1
grey[4] => normal~0.IN0
grey[4] => norm[4].DATAIN
norm[0] <= normal~3.DB_MAX_OUTPUT_PORT_TYPE
norm[1] <= normal~2.DB_MAX_OUTPUT_PORT_TYPE
norm[2] <= normal~1.DB_MAX_OUTPUT_PORT_TYPE
norm[3] <= normal~0.DB_MAX_OUTPUT_PORT_TYPE
norm[4] <= grey[4].DB_MAX_OUTPUT_PORT_TYPE


|fifotop|full_empty:inst3|g2b:inst8
grey[0] => normal~3.IN0
grey[1] => normal~2.IN0
grey[2] => normal~1.IN0
grey[3] => normal~0.IN1
grey[4] => normal~0.IN0
grey[4] => norm[4].DATAIN
norm[0] <= normal~3.DB_MAX_OUTPUT_PORT_TYPE
norm[1] <= normal~2.DB_MAX_OUTPUT_PORT_TYPE
norm[2] <= normal~1.DB_MAX_OUTPUT_PORT_TYPE
norm[3] <= normal~0.DB_MAX_OUTPUT_PORT_TYPE
norm[4] <= grey[4].DB_MAX_OUTPUT_PORT_TYPE


|fifotop|full_empty:inst3|sync:inst7
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
clk => addr_s[4]~reg0.CLK
clk => addr_s[3]~reg0.CLK
clk => addr_s[2]~reg0.CLK
clk => addr_s[1]~reg0.CLK
clk => addr_s[0]~reg0.CLK
addr_a[0] => temp[0].DATAIN
addr_a[1] => temp[1].DATAIN
addr_a[2] => temp[2].DATAIN
addr_a[3] => temp[3].DATAIN
addr_a[4] => temp[4].DATAIN
addr_s[0] <= addr_s[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_s[1] <= addr_s[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_s[2] <= addr_s[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_s[3] <= addr_s[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_s[4] <= addr_s[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fifotop|full_empty:inst3|full_cmp:inst4
wr_addr[0] => Equal0.IN3
wr_addr[1] => Equal0.IN2
wr_addr[2] => Equal0.IN1
wr_addr[3] => Equal0.IN0
wr_addr[4] => full~0.IN0
rd_addr[0] => Equal0.IN7
rd_addr[1] => Equal0.IN6
rd_addr[2] => Equal0.IN5
rd_addr[3] => Equal0.IN4
rd_addr[4] => full~0.IN1
full <= full~1.DB_MAX_OUTPUT_PORT_TYPE


|fifotop|full_empty:inst3|g2b:inst6
grey[0] => normal~3.IN0
grey[1] => normal~2.IN0
grey[2] => normal~1.IN0
grey[3] => normal~0.IN1
grey[4] => normal~0.IN0
grey[4] => norm[4].DATAIN
norm[0] <= normal~3.DB_MAX_OUTPUT_PORT_TYPE
norm[1] <= normal~2.DB_MAX_OUTPUT_PORT_TYPE
norm[2] <= normal~1.DB_MAX_OUTPUT_PORT_TYPE
norm[3] <= normal~0.DB_MAX_OUTPUT_PORT_TYPE
norm[4] <= grey[4].DB_MAX_OUTPUT_PORT_TYPE


|fifotop|full_empty:inst3|sync:inst
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
clk => addr_s[4]~reg0.CLK
clk => addr_s[3]~reg0.CLK
clk => addr_s[2]~reg0.CLK
clk => addr_s[1]~reg0.CLK
clk => addr_s[0]~reg0.CLK
addr_a[0] => temp[0].DATAIN
addr_a[1] => temp[1].DATAIN
addr_a[2] => temp[2].DATAIN
addr_a[3] => temp[3].DATAIN
addr_a[4] => temp[4].DATAIN
addr_s[0] <= addr_s[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_s[1] <= addr_s[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_s[2] <= addr_s[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_s[3] <= addr_s[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_s[4] <= addr_s[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fifotop|full_empty:inst3|g2b:inst3
grey[0] => normal~3.IN0
grey[1] => normal~2.IN0
grey[2] => normal~1.IN0
grey[3] => normal~0.IN1
grey[4] => normal~0.IN0
grey[4] => norm[4].DATAIN
norm[0] <= normal~3.DB_MAX_OUTPUT_PORT_TYPE
norm[1] <= normal~2.DB_MAX_OUTPUT_PORT_TYPE
norm[2] <= normal~1.DB_MAX_OUTPUT_PORT_TYPE
norm[3] <= normal~0.DB_MAX_OUTPUT_PORT_TYPE
norm[4] <= grey[4].DB_MAX_OUTPUT_PORT_TYPE


|fifotop|gray:inst6
clk => new_q[4].CLK
clk => new_q[3].CLK
clk => new_q[2].CLK
clk => new_q[1].CLK
clk => new_q[0].CLK
en => new_q[0].ENA
en => new_q[1].ENA
en => new_q[2].ENA
en => new_q[3].ENA
en => new_q[4].ENA
q[0] <= new_q[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= new_q[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= new_q[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= new_q[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= new_q[4].DB_MAX_OUTPUT_PORT_TYPE


|fifotop|gray:inst
clk => new_q[4].CLK
clk => new_q[3].CLK
clk => new_q[2].CLK
clk => new_q[1].CLK
clk => new_q[0].CLK
en => new_q[0].ENA
en => new_q[1].ENA
en => new_q[2].ENA
en => new_q[3].ENA
en => new_q[4].ENA
q[0] <= new_q[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= new_q[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= new_q[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= new_q[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= new_q[4].DB_MAX_OUTPUT_PORT_TYPE


|fifotop|ramdp:inst4
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]