full_empty.tan.qmsg

来自「基于FPGA编写的VHDL语言」· QMSG 代码 · 共 14 行 · 第 1/4 页

{ "Info" "ITDB_FULL_TCO_RESULT" "rdclk rden_vaild sync:inst7\|addr_s\[0\] 15.067 ns register " "Info: tco from clock \"rdclk\" to destination pin \"rden_vaild\" through register \"sync:inst7\|addr_s\[0\]\" is 15.067 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclk source 2.871 ns + Longest register " "Info: + Longest clock path from clock \"rdclk\" to source register is 2.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns rdclk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns rdclk~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rdclk rdclk~clkctrl } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.666 ns) 2.871 ns sync:inst7\|addr_s\[0\] 3 REG LCFF_X28_Y18_N25 1 " "Info: 3: + IC(0.926 ns) + CELL(0.666 ns) = 2.871 ns; Loc. = LCFF_X28_Y18_N25; Fanout = 1; REG Node = 'sync:inst7\|addr_s\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { rdclk~clkctrl sync:inst7|addr_s[0] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.90 % ) " "Info: Total cell delay = 1.806 ns ( 62.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 37.10 % ) " "Info: Total interconnect delay = 1.065 ns ( 37.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { rdclk rdclk~clkctrl sync:inst7|addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.871 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|addr_s[0] {} } { 0.000ns 0.000ns 0.139ns 0.926ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.892 ns + Longest register pin " "Info: + Longest register to pin delay is 11.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sync:inst7\|addr_s\[0\] 1 REG LCFF_X28_Y18_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y18_N25; Fanout = 1; REG Node = 'sync:inst7\|addr_s\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sync:inst7|addr_s[0] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.270 ns) + CELL(0.646 ns) 4.916 ns empty_cmp:inst5\|Equal0~132 2 COMB LCCOMB_X1_Y16_N28 1 " "Info: 2: + IC(4.270 ns) + CELL(0.646 ns) = 4.916 ns; Loc. = LCCOMB_X1_Y16_N28; Fanout = 1; COMB Node = 'empty_cmp:inst5\|Equal0~132'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { sync:inst7|addr_s[0] empty_cmp:inst5|Equal0~132 } "NODE_NAME" } } { "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.370 ns) 5.959 ns empty_cmp:inst5\|Equal0~134 3 COMB LCCOMB_X1_Y16_N10 2 " "Info: 3: + IC(0.673 ns) + CELL(0.370 ns) = 5.959 ns; Loc. = LCCOMB_X1_Y16_N10; Fanout = 2; COMB Node = 'empty_cmp:inst5\|Equal0~134'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.043 ns" { empty_cmp:inst5|Equal0~132 empty_cmp:inst5|Equal0~134 } "NODE_NAME" } } { "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.406 ns) + CELL(0.650 ns) 7.015 ns inst11 4 COMB LCCOMB_X1_Y16_N22 1 " "Info: 4: + IC(0.406 ns) + CELL(0.650 ns) = 7.015 ns; Loc. = LCCOMB_X1_Y16_N22; Fanout = 1; COMB Node = 'inst11'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.056 ns" { empty_cmp:inst5|Equal0~134 inst11 } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 576 760 824 624 "inst11" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.601 ns) + CELL(3.276 ns) 11.892 ns rden_vaild 5 PIN PIN_56 0 " "Info: 5: + IC(1.601 ns) + CELL(3.276 ns) = 11.892 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'rden_vaild'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.877 ns" { inst11 rden_vaild } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 592 880 1056 608 "rden_vaild" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.942 ns ( 41.56 % ) " "Info: Total cell delay = 4.942 ns ( 41.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.950 ns ( 58.44 % ) " "Info: Total interconnect delay = 6.950 ns ( 58.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "11.892 ns" { sync:inst7|addr_s[0] empty_cmp:inst5|Equal0~132 empty_cmp:inst5|Equal0~134 inst11 rden_vaild } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "11.892 ns" { sync:inst7|addr_s[0] {} empty_cmp:inst5|Equal0~132 {} empty_cmp:inst5|Equal0~134 {} inst11 {} rden_vaild {} } { 0.000ns 4.270ns 0.673ns 0.406ns 1.601ns } { 0.000ns 0.646ns 0.370ns 0.650ns 3.276ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { rdclk rdclk~clkctrl sync:inst7|addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.871 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|addr_s[0] {} } { 0.000ns 0.000ns 0.139ns 0.926ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "11.892 ns" { sync:inst7|addr_s[0] empty_cmp:inst5|Equal0~132 empty_cmp:inst5|Equal0~134 inst11 rden_vaild } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "11.892 ns" { sync:inst7|addr_s[0] {} empty_cmp:inst5|Equal0~132 {} empty_cmp:inst5|Equal0~134 {} inst11 {} rden_vaild {} } { 0.000ns 4.270ns 0.673ns 0.406ns 1.601ns } { 0.000ns 0.646ns 0.370ns 0.650ns 3.276ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "rd_addr_grey\[3\] rden_vaild 15.032 ns Longest " "Info: Longest tpd from source pin \"rd_addr_grey\[3\]\" to destination pin \"rden_vaild\" is 15.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns rd_addr_grey\[3\] 1 PIN PIN_197 2 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_197; Fanout = 2; PIN Node = 'rd_addr_grey\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd_addr_grey[3] } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 528 -72 104 544 "rd_addr_grey\[4..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.508 ns) + CELL(0.623 ns) 8.105 ns empty_cmp:inst5\|Equal0~131 2 COMB LCCOMB_X1_Y16_N2 3 " "Info: 2: + IC(6.508 ns) + CELL(0.623 ns) = 8.105 ns; Loc. = LCCOMB_X1_Y16_N2; Fanout = 3; COMB Node = 'empty_cmp:inst5\|Equal0~131'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.131 ns" { rd_addr_grey[3] empty_cmp:inst5|Equal0~131 } "NODE_NAME" } } { "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.616 ns) 9.099 ns empty_cmp:inst5\|Equal0~134 3 COMB LCCOMB_X1_Y16_N10 2 " "Info: 3: + IC(0.378 ns) + CELL(0.616 ns) = 9.099 ns; Loc. = LCCOMB_X1_Y16_N10; Fanout = 2; COMB Node = 'empty_cmp:inst5\|Equal0~134'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { empty_cmp:inst5|Equal0~131 empty_cmp:inst5|Equal0~134 } "NODE_NAME" } } { "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.406 ns) + CELL(0.650 ns) 10.155 ns inst11 4 COMB LCCOMB_X1_Y16_N22 1 " "Info: 4: + IC(0.406 ns) + CELL(0.650 ns) = 10.155 ns; Loc. = LCCOMB_X1_Y16_N22; Fanout = 1; COMB Node = 'inst11'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.056 ns" { empty_cmp:inst5|Equal0~134 inst11 } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 576 760 824 624 "inst11" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.601 ns) + CELL(3.276 ns) 15.032 ns rden_vaild 5 PIN PIN_56 0 " "Info: 5: + IC(1.601 ns) + CELL(3.276 ns) = 15.032 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'rden_vaild'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.877 ns" { inst11 rden_vaild } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 592 880 1056 608 "rden_vaild" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.139 ns ( 40.84 % ) " "Info: Total cell delay = 6.139 ns ( 40.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.893 ns ( 59.16 % ) " "Info: Total interconnect delay = 8.893 ns ( 59.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "15.032 ns" { rd_addr_grey[3] empty_cmp:inst5|Equal0~131 empty_cmp:inst5|Equal0~134 inst11 rden_vaild } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "15.032 ns" { rd_addr_grey[3] {} rd_addr_grey[3]~combout {} empty_cmp:inst5|Equal0~131 {} empty_cmp:inst5|Equal0~134 {} inst11 {} rden_vaild {} } { 0.000ns 0.000ns 6.508ns 0.378ns 0.406ns 1.601ns } { 0.000ns 0.974ns 0.623ns 0.616ns 0.650ns 3.276ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "sync:inst7\|temp\[4\] wr_addr_gery\[4\] rdclk 0.217 ns register " "Info: th for register \"sync:inst7\|temp\[4\]\" (data pin = \"wr_addr_gery\[4\]\", clock pin = \"rdclk\") is 0.217 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclk destination 2.864 ns + Longest register " "Info: + Longest clock path from clock \"rdclk\" to destination register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns rdclk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns rdclk~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rdclk rdclk~clkctrl } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.666 ns) 2.864 ns sync:inst7\|temp\[4\] 3 REG LCFF_X1_Y16_N15 1 " "Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X1_Y16_N15; Fanout = 1; REG Node = 'sync:inst7\|temp\[4\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { rdclk~clkctrl sync:inst7|temp[4] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.06 % ) " "Info: Total cell delay = 1.806 ns ( 63.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.058 ns ( 36.94 % ) " "Info: Total interconnect delay = 1.058 ns ( 36.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|temp[4] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|temp[4] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.953 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.953 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns wr_addr_gery\[4\] 1 PIN PIN_28 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_28; Fanout = 2; PIN Node = 'wr_addr_gery\[4\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_addr_gery[4] } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 96 -32 152 112 "wr_addr_gery\[4..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.353 ns) + CELL(0.460 ns) 2.953 ns sync:inst7\|temp\[4\] 2 REG LCFF_X1_Y16_N15 1 " "Info: 2: + IC(1.353 ns) + CELL(0.460 ns) = 2.953 ns; Loc. = LCFF_X1_Y16_N15; Fanout = 1; REG Node = 'sync:inst7\|temp\[4\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.813 ns" { wr_addr_gery[4] sync:inst7|temp[4] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.18 % ) " "Info: Total cell delay = 1.600 ns ( 54.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.353 ns ( 45.82 % ) " "Info: Total interconnect delay = 1.353 ns ( 45.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.953 ns" { wr_addr_gery[4] sync:inst7|temp[4] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.953 ns" { wr_addr_gery[4] {} wr_addr_gery[4]~combout {} sync:inst7|temp[4] {} } { 0.000ns 0.000ns 1.353ns } { 0.000ns 1.140ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|temp[4] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|temp[4] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.953 ns" { wr_addr_gery[4] sync:inst7|temp[4] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.953 ns" { wr_addr_gery[4] {} wr_addr_gery[4]~combout {} sync:inst7|temp[4] {} } { 0.000ns 0.000ns 1.353ns } { 0.000ns 1.140ns 0.460ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}