full_empty.tan.qmsg

来自「基于FPGA编写的VHDL语言」· QMSG 代码 · 共 14 行 · 第 1/4 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "rdclk " "Info: Assuming node \"rdclk\" is an undefined clock" {  } { { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } } { "d:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "rdclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wrclk " "Info: Assuming node \"wrclk\" is an undefined clock" {  } { { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 264 -40 128 280 "wrclk" "" } } } } { "d:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "wrclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "rdclk register register sync:inst7\|temp\[3\] sync:inst7\|addr_s\[3\] 340.02 MHz Internal " "Info: Clock \"rdclk\" Internal fmax is restricted to 340.02 MHz between source register \"sync:inst7\|temp\[3\]\" and destination register \"sync:inst7\|addr_s\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.908 ns + Longest register register " "Info: + Longest register to register delay is 0.908 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sync:inst7\|temp\[3\] 1 REG LCFF_X1_Y16_N21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y16_N21; Fanout = 1; REG Node = 'sync:inst7\|temp\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sync:inst7|temp[3] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.460 ns) 0.908 ns sync:inst7\|addr_s\[3\] 2 REG LCFF_X1_Y16_N3 1 " "Info: 2: + IC(0.448 ns) + CELL(0.460 ns) = 0.908 ns; Loc. = LCFF_X1_Y16_N3; Fanout = 1; REG Node = 'sync:inst7\|addr_s\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.908 ns" { sync:inst7|temp[3] sync:inst7|addr_s[3] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.460 ns ( 50.66 % ) " "Info: Total cell delay = 0.460 ns ( 50.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.448 ns ( 49.34 % ) " "Info: Total interconnect delay = 0.448 ns ( 49.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.908 ns" { sync:inst7|temp[3] sync:inst7|addr_s[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.908 ns" { sync:inst7|temp[3] {} sync:inst7|addr_s[3] {} } { 0.000ns 0.448ns } { 0.000ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclk destination 2.864 ns + Shortest register " "Info: + Shortest clock path from clock \"rdclk\" to destination register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns rdclk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns rdclk~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rdclk rdclk~clkctrl } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.666 ns) 2.864 ns sync:inst7\|addr_s\[3\] 3 REG LCFF_X1_Y16_N3 1 " "Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X1_Y16_N3; Fanout = 1; REG Node = 'sync:inst7\|addr_s\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { rdclk~clkctrl sync:inst7|addr_s[3] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.06 % ) " "Info: Total cell delay = 1.806 ns ( 63.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.058 ns ( 36.94 % ) " "Info: Total interconnect delay = 1.058 ns ( 36.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|addr_s[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|addr_s[3] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclk source 2.864 ns - Longest register " "Info: - Longest clock path from clock \"rdclk\" to source register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns rdclk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns rdclk~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rdclk rdclk~clkctrl } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.666 ns) 2.864 ns sync:inst7\|temp\[3\] 3 REG LCFF_X1_Y16_N21 1 " "Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X1_Y16_N21; Fanout = 1; REG Node = 'sync:inst7\|temp\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { rdclk~clkctrl sync:inst7|temp[3] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.06 % ) " "Info: Total cell delay = 1.806 ns ( 63.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.058 ns ( 36.94 % ) " "Info: Total interconnect delay = 1.058 ns ( 36.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|temp[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|temp[3] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|addr_s[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|addr_s[3] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|temp[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|temp[3] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.908 ns" { sync:inst7|temp[3] sync:inst7|addr_s[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.908 ns" { sync:inst7|temp[3] {} sync:inst7|addr_s[3] {} } { 0.000ns 0.448ns } { 0.000ns 0.460ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|addr_s[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|addr_s[3] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|temp[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|temp[3] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sync:inst7|addr_s[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { sync:inst7|addr_s[3] {} } {  } {  } "" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "wrclk register register sync:inst\|temp\[0\] sync:inst\|addr_s\[0\] 340.02 MHz Internal " "Info: Clock \"wrclk\" Internal fmax is restricted to 340.02 MHz between source register \"sync:inst\|temp\[0\]\" and destination register \"sync:inst\|addr_s\[0\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.217 ns + Longest register register " "Info: + Longest register to register delay is 1.217 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sync:inst\|temp\[0\] 1 REG LCFF_X2_Y16_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y16_N1; Fanout = 1; REG Node = 'sync:inst\|temp\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sync:inst|temp[0] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.460 ns) 1.217 ns sync:inst\|addr_s\[0\] 2 REG LCFF_X1_Y16_N31 1 " "Info: 2: + IC(0.757 ns) + CELL(0.460 ns) = 1.217 ns; Loc. = LCFF_X1_Y16_N31; Fanout = 1; REG Node = 'sync:inst\|addr_s\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { sync:inst|temp[0] sync:inst|addr_s[0] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.460 ns ( 37.80 % ) " "Info: Total cell delay = 0.460 ns ( 37.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.757 ns ( 62.20 % ) " "Info: Total interconnect delay = 0.757 ns ( 62.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { sync:inst|temp[0] sync:inst|addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "1.217 ns" { sync:inst|temp[0] {} sync:inst|addr_s[0] {} } { 0.000ns 0.757ns } { 0.000ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclk destination 2.854 ns + Shortest register " "Info: + Shortest clock path from clock \"wrclk\" to destination register is 2.854 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns wrclk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'wrclk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrclk } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 264 -40 128 280 "wrclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns wrclk~clkctrl 2 COMB CLKCTRL_G1 10 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'wrclk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { wrclk wrclk~clkctrl } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 264 -40 128 280 "wrclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.666 ns) 2.854 ns sync:inst\|addr_s\[0\] 3 REG LCFF_X1_Y16_N31 1 " "Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.854 ns; Loc. = LCFF_X1_Y16_N31; Fanout = 1; REG Node = 'sync:inst\|addr_s\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { wrclk~clkctrl sync:inst|addr_s[0] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.796 ns ( 62.93 % ) " "Info: Total cell delay = 1.796 ns ( 62.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.058 ns ( 37.07 % ) " "Info: Total interconnect delay = 1.058 ns ( 37.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.854 ns" { wrclk wrclk~clkctrl sync:inst|addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.854 ns" { wrclk {} wrclk~combout {} wrclk~clkctrl {} sync:inst|addr_s[0] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclk source 2.853 ns - Longest register " "Info: - Longest clock path from clock \"wrclk\" to source register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns wrclk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'wrclk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrclk } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 264 -40 128 280 "wrclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns wrclk~clkctrl 2 COMB CLKCTRL_G1 10 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'wrclk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { wrclk wrclk~clkctrl } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 264 -40 128 280 "wrclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.666 ns) 2.853 ns sync:inst\|temp\[0\] 3 REG LCFF_X2_Y16_N1 1 " "Info: 3: + IC(0.918 ns) + CELL(0.666 ns) = 2.853 ns; Loc. = LCFF_X2_Y16_N1; Fanout = 1; REG Node = 'sync:inst\|temp\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { wrclk~clkctrl sync:inst|temp[0] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.796 ns ( 62.95 % ) " "Info: Total cell delay = 1.796 ns ( 62.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.057 ns ( 37.05 % ) " "Info: Total interconnect delay = 1.057 ns ( 37.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { wrclk wrclk~clkctrl sync:inst|temp[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { wrclk {} wrclk~combout {} wrclk~clkctrl {} sync:inst|temp[0] {} } { 0.000ns 0.000ns 0.139ns 0.918ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.854 ns" { wrclk wrclk~clkctrl sync:inst|addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.854 ns" { wrclk {} wrclk~combout {} wrclk~clkctrl {} sync:inst|addr_s[0] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { wrclk wrclk~clkctrl sync:inst|temp[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { wrclk {} wrclk~combout {} wrclk~clkctrl {} sync:inst|temp[0] {} } { 0.000ns 0.000ns 0.139ns 0.918ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { sync:inst|temp[0] sync:inst|addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "1.217 ns" { sync:inst|temp[0] {} sync:inst|addr_s[0] {} } { 0.000ns 0.757ns } { 0.000ns 0.460ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.854 ns" { wrclk wrclk~clkctrl sync:inst|addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.854 ns" { wrclk {} wrclk~combout {} wrclk~clkctrl {} sync:inst|addr_s[0] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { wrclk wrclk~clkctrl sync:inst|temp[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { wrclk {} wrclk~combout {} wrclk~clkctrl {} sync:inst|temp[0] {} } { 0.000ns 0.000ns 0.139ns 0.918ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sync:inst|addr_s[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { sync:inst|addr_s[0] {} } {  } {  } "" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 26 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sync:inst7\|temp\[2\] wr_addr_gery\[2\] rdclk 5.518 ns register " "Info: tsu for register \"sync:inst7\|temp\[2\]\" (data pin = \"wr_addr_gery\[2\]\", clock pin = \"rdclk\") is 5.518 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.422 ns + Longest pin register " "Info: + Longest pin to register delay is 8.422 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns wr_addr_gery\[2\] 1 PIN PIN_74 2 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_74; Fanout = 2; PIN Node = 'wr_addr_gery\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_addr_gery[2] } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 96 -32 152 112 "wr_addr_gery\[4..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.998 ns) + CELL(0.460 ns) 8.422 ns sync:inst7\|temp\[2\] 2 REG LCFF_X1_Y16_N17 1 " "Info: 2: + IC(6.998 ns) + CELL(0.460 ns) = 8.422 ns; Loc. = LCFF_X1_Y16_N17; Fanout = 1; REG Node = 'sync:inst7\|temp\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.458 ns" { wr_addr_gery[2] sync:inst7|temp[2] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.424 ns ( 16.91 % ) " "Info: Total cell delay = 1.424 ns ( 16.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.998 ns ( 83.09 % ) " "Info: Total interconnect delay = 6.998 ns ( 83.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.422 ns" { wr_addr_gery[2] sync:inst7|temp[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.422 ns" { wr_addr_gery[2] {} wr_addr_gery[2]~combout {} sync:inst7|temp[2] {} } { 0.000ns 0.000ns 6.998ns } { 0.000ns 0.964ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclk destination 2.864 ns - Shortest register " "Info: - Shortest clock path from clock \"rdclk\" to destination register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns rdclk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns rdclk~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rdclk rdclk~clkctrl } "NODE_NAME" } } { "full_empty.bdf" "" { Schematic "E:/workroom2/quartusIIex/fifotop/full_empty.bdf" { { 400 -64 104 416 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.666 ns) 2.864 ns sync:inst7\|temp\[2\] 3 REG LCFF_X1_Y16_N17 1 " "Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X1_Y16_N17; Fanout = 1; REG Node = 'sync:inst7\|temp\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { rdclk~clkctrl sync:inst7|temp[2] } "NODE_NAME" } } { "sync.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/sync.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.06 % ) " "Info: Total cell delay = 1.806 ns ( 63.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.058 ns ( 36.94 % ) " "Info: Total interconnect delay = 1.058 ns ( 36.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|temp[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|temp[2] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.422 ns" { wr_addr_gery[2] sync:inst7|temp[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.422 ns" { wr_addr_gery[2] {} wr_addr_gery[2]~combout {} sync:inst7|temp[2] {} } { 0.000ns 0.000ns 6.998ns } { 0.000ns 0.964ns 0.460ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { rdclk rdclk~clkctrl sync:inst7|temp[2] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { rdclk {} rdclk~combout {} rdclk~clkctrl {} sync:inst7|temp[2] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}