full_cmp.fit.summary

来自「基于FPGA编写的VHDL语言」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Thu Apr 09 15:49:14 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : full_cmp
Top-level Entity Name : full_cmp
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
Total logic elements : 3 / 8,256 ( < 1 % )
    Total combinational functions : 3 / 8,256 ( < 1 % )
    Dedicated logic registers : 0 / 8,256 ( 0 % )
Total registers : 0
Total pins : 9 / 138 ( 7 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )