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📄 fifotop.sim.rpt

📁 基于FPGA编写的VHDL语言
💻 RPT
📖 第 1 页 / 共 3 页
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; |fifotop|wr_clk~clkctrl                                                                          ; |fifotop|wr_clk~clkctrl                                                                    ; outclk           ;
; |fifotop|rd_clk~clkctrl                                                                          ; |fifotop|rd_clk~clkctrl                                                                    ; outclk           ;
; |fifotop|full_empty:inst3|sync:inst7|temp[0]~feeder                                              ; |fifotop|full_empty:inst3|sync:inst7|temp[0]~feeder                                        ; combout          ;
; |fifotop|full_empty:inst3|sync:inst7|temp[2]~feeder                                              ; |fifotop|full_empty:inst3|sync:inst7|temp[2]~feeder                                        ; combout          ;
; |fifotop|full_empty:inst3|sync:inst|temp[1]~feeder                                               ; |fifotop|full_empty:inst3|sync:inst|temp[1]~feeder                                         ; combout          ;
; |fifotop|full_empty:inst3|sync:inst|temp[2]~feeder                                               ; |fifotop|full_empty:inst3|sync:inst|temp[2]~feeder                                         ; combout          ;
; |fifotop|full_empty:inst3|sync:inst|addr_s[2]~feeder                                             ; |fifotop|full_empty:inst3|sync:inst|addr_s[2]~feeder                                       ; combout          ;
+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                        ; Output Port Name                                                                           ; Output Port Type ;
+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0 ; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|q_b[4] ; portbdataout4    ;
; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0 ; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|q_b[5] ; portbdataout5    ;
; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0 ; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|q_b[6] ; portbdataout6    ;
; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0 ; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|q_b[7] ; portbdataout7    ;
; |fifotop|full_empty:inst3|inst10                                                                 ; |fifotop|full_empty:inst3|inst10                                                           ; combout          ;
; |fifotop|q[7]                                                                                    ; |fifotop|q[7]                                                                              ; padio            ;
; |fifotop|q[6]                                                                                    ; |fifotop|q[6]                                                                              ; padio            ;
; |fifotop|q[5]                                                                                    ; |fifotop|q[5]                                                                              ; padio            ;
; |fifotop|q[4]                                                                                    ; |fifotop|q[4]                                                                              ; padio            ;
; |fifotop|wren                                                                                    ; |fifotop|wren~corein                                                                       ; combout          ;
; |fifotop|data[7]                                                                                 ; |fifotop|data[7]~corein                                                                    ; combout          ;
+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                        ; Output Port Name                                                                           ; Output Port Type ;
+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0 ; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|q_b[3] ; portbdataout3    ;
; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0 ; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|q_b[4] ; portbdataout4    ;
; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0 ; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|q_b[5] ; portbdataout5    ;
; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0 ; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|q_b[6] ; portbdataout6    ;
; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|ram_block1a0 ; |fifotop|ramdp:inst4|altsyncram:altsyncram_component|altsyncram_puo1:auto_generated|q_b[7] ; portbdataout7    ;
; |fifotop|gray:inst|new_q[4]                                                                      ; |fifotop|gray:inst|new_q[4]                                                                ; regout           ;
; |fifotop|gray:inst|new_q[3]                                                                      ; |fifotop|gray:inst|new_q[3]                                                                ; regout           ;
; |fifotop|full_empty:inst3|sync:inst|addr_s[4]                                                    ; |fifotop|full_empty:inst3|sync:inst|addr_s[4]                                              ; regout           ;
; |fifotop|full_empty:inst3|sync:inst|addr_s[3]                                                    ; |fifotop|full_empty:inst3|sync:inst|addr_s[3]                                              ; regout           ;
; |fifotop|gray:inst6|new_q[4]                                                                     ; |fifotop|gray:inst6|new_q[4]                                                               ; regout           ;
; |fifotop|gray:inst6|new_q[3]                                                                     ; |fifotop|gray:inst6|new_q[3]                                                               ; regout           ;
; |fifotop|full_empty:inst3|sync:inst7|addr_s[4]                                                   ; |fifotop|full_empty:inst3|sync:inst7|addr_s[4]                                             ; regout           ;
; |fifotop|full_empty:inst3|sync:inst7|addr_s[3]                                                   ; |fifotop|full_empty:inst3|sync:inst7|addr_s[3]                                             ; regout           ;
; |fifotop|full_empty:inst3|sync:inst|temp[4]                                                      ; |fifotop|full_empty:inst3|sync:inst|temp[4]                                                ; regout           ;
; |fifotop|full_empty:inst3|sync:inst|temp[3]                                                      ; |fifotop|full_empty:inst3|sync:inst|temp[3]                                                ; regout           ;
; |fifotop|full_empty:inst3|sync:inst7|temp[4]                                                     ; |fifotop|full_empty:inst3|sync:inst7|temp[4]                                               ; regout           ;
; |fifotop|full_empty:inst3|sync:inst7|temp[3]                                                     ; |fifotop|full_empty:inst3|sync:inst7|temp[3]                                               ; regout           ;
; |fifotop|q[7]                                                                                    ; |fifotop|q[7]                                                                              ; padio            ;
; |fifotop|q[6]                                                                                    ; |fifotop|q[6]                                                                              ; padio            ;
; |fifotop|q[5]                                                                                    ; |fifotop|q[5]                                                                              ; padio            ;
; |fifotop|q[4]                                                                                    ; |fifotop|q[4]                                                                              ; padio            ;
; |fifotop|q[3]                                                                                    ; |fifotop|q[3]                                                                              ; padio            ;
; |fifotop|data[7]                                                                                 ; |fifotop|data[7]~corein                                                                    ; combout          ;
; |fifotop|data[6]                                                                                 ; |fifotop|data[6]~corein                                                                    ; combout          ;
; |fifotop|full_empty:inst3|sync:inst7|temp[4]~feeder                                              ; |fifotop|full_empty:inst3|sync:inst7|temp[4]~feeder                                        ; combout          ;
; |fifotop|full_empty:inst3|sync:inst|temp[4]~feeder                                               ; |fifotop|full_empty:inst3|sync:inst|temp[4]~feeder                                         ; combout          ;
+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Tue Apr 21 21:55:30 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off fifotop -c fifotop
Info: Using vector source file "E:/workroom2/quartusIIex/fifotop/fifotop.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      72.82 %
Info: Number of transitions in simulation is 1171
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 118 megabytes
    Info: Processing ended: Tue Apr 21 21:55:31 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


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