sync.vhd.bak

基于FPGA编写的VHDL语言

--sync.vhd
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity sync is
generic(n:integer:=4);
 port(
     --
     clk:in std_logic;
     --
     addr_a:in std_logic_vector(n-1 downto 0);
     --
     addr_s:out std_logic_vector(n-1 downto 0)
     );
end sync;

architecture behave of sync is
signal temp:std_logic_vector(n-1 downto 0);
begin
  process(clk)
    begin
    addr_s<=addr_a;
    if rising_edge(clk) then
    temp <= addr_a;
    addr_s <= temp;

    end if;
   end process;
end behave;