full_cmp.vhd

来自「基于FPGA编写的VHDL语言」· VHDL 代码 · 共 28 行

--full_cmp.vhd
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity full_cmp is
generic(n:integer:=4);
port(
    --
    wr_addr:in std_logic_vector(n-1 downto 0);
    --
    rd_addr:in std_logic_vector(n-1 downto 0);
    --
    full :out std_logic
);
end full_cmp;

architecture behave of full_cmp is

begin
  full<='1'when (wr_addr(n-1)/=rd_addr(n-1))and
   (wr_addr(n-2 downto 0)= rd_addr(n-2 downto 0))else
   '0';
end behave;