full_empty.tan.summary

来自「基于FPGA编写的VHDL语言」· SUMMARY 代码 · 共 77 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.518 ns
From           : wr_addr_gery[2]
To             : sync:inst7|temp[2]
From Clock     : --
To Clock       : rdclk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.067 ns
From           : sync:inst7|addr_s[0]
To             : rden_vaild
From Clock     : rdclk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 15.032 ns
From           : rd_addr_grey[3]
To             : rden_vaild
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.217 ns
From           : wr_addr_gery[4]
To             : sync:inst7|temp[4]
From Clock     : --
To Clock       : rdclk
Failed Paths   : 0

Type           : Clock Setup: 'wrclk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 340.02 MHz ( period = 2.941 ns )
From           : sync:inst|temp[0]
To             : sync:inst|addr_s[0]
From Clock     : wrclk
To Clock       : wrclk
Failed Paths   : 0

Type           : Clock Setup: 'rdclk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 340.02 MHz ( period = 2.941 ns )
From           : sync:inst7|temp[2]
To             : sync:inst7|addr_s[2]
From Clock     : rdclk
To Clock       : rdclk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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