full_empty.tan.rpt

基于FPGA编写的VHDL语言

Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Fri Apr 10 20:23:34 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off full_empty -c full_empty --timing_analysis_only
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "rdclk" is an undefined clock
    Info: Assuming node "wrclk" is an undefined clock
Info: Clock "rdclk" Internal fmax is restricted to 340.02 MHz between source register "sync:inst7|temp[3]" and destination register "sync:inst7|addr_s[3]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.908 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y16_N21; Fanout = 1; REG Node = 'sync:inst7|temp[3]'
            Info: 2: + IC(0.448 ns) + CELL(0.460 ns) = 0.908 ns; Loc. = LCFF_X1_Y16_N3; Fanout = 1; REG Node = 'sync:inst7|addr_s[3]'
            Info: Total cell delay = 0.460 ns ( 50.66 % )
            Info: Total interconnect delay = 0.448 ns ( 49.34 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "rdclk" to destination register is 2.864 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'
                Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X1_Y16_N3; Fanout = 1; REG Node = 'sync:inst7|addr_s[3]'
                Info: Total cell delay = 1.806 ns ( 63.06 % )
                Info: Total interconnect delay = 1.058 ns ( 36.94 % )
            Info: - Longest clock path from clock "rdclk" to source register is 2.864 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'
                Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X1_Y16_N21; Fanout = 1; REG Node = 'sync:inst7|temp[3]'
                Info: Total cell delay = 1.806 ns ( 63.06 % )
                Info: Total interconnect delay = 1.058 ns ( 36.94 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: Clock "wrclk" Internal fmax is restricted to 340.02 MHz between source register "sync:inst|temp[0]" and destination register "sync:inst|addr_s[0]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.217 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y16_N1; Fanout = 1; REG Node = 'sync:inst|temp[0]'
            Info: 2: + IC(0.757 ns) + CELL(0.460 ns) = 1.217 ns; Loc. = LCFF_X1_Y16_N31; Fanout = 1; REG Node = 'sync:inst|addr_s[0]'
            Info: Total cell delay = 0.460 ns ( 37.80 % )
            Info: Total interconnect delay = 0.757 ns ( 62.20 % )
        Info: - Smallest clock skew is 0.001 ns
            Info: + Shortest clock path from clock "wrclk" to destination register is 2.854 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'wrclk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'wrclk~clkctrl'
                Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.854 ns; Loc. = LCFF_X1_Y16_N31; Fanout = 1; REG Node = 'sync:inst|addr_s[0]'
                Info: Total cell delay = 1.796 ns ( 62.93 % )
                Info: Total interconnect delay = 1.058 ns ( 37.07 % )
            Info: - Longest clock path from clock "wrclk" to source register is 2.853 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'wrclk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'wrclk~clkctrl'
                Info: 3: + IC(0.918 ns) + CELL(0.666 ns) = 2.853 ns; Loc. = LCFF_X2_Y16_N1; Fanout = 1; REG Node = 'sync:inst|temp[0]'
                Info: Total cell delay = 1.796 ns ( 62.95 % )
                Info: Total interconnect delay = 1.057 ns ( 37.05 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "sync:inst7|temp[2]" (data pin = "wr_addr_gery[2]", clock pin = "rdclk") is 5.518 ns
    Info: + Longest pin to register delay is 8.422 ns
        Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_74; Fanout = 2; PIN Node = 'wr_addr_gery[2]'
        Info: 2: + IC(6.998 ns) + CELL(0.460 ns) = 8.422 ns; Loc. = LCFF_X1_Y16_N17; Fanout = 1; REG Node = 'sync:inst7|temp[2]'
        Info: Total cell delay = 1.424 ns ( 16.91 % )
        Info: Total interconnect delay = 6.998 ns ( 83.09 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "rdclk" to destination register is 2.864 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'
        Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X1_Y16_N17; Fanout = 1; REG Node = 'sync:inst7|temp[2]'
        Info: Total cell delay = 1.806 ns ( 63.06 % )
        Info: Total interconnect delay = 1.058 ns ( 36.94 % )
Info: tco from clock "rdclk" to destination pin "rden_vaild" through register "sync:inst7|addr_s[0]" is 15.067 ns
    Info: + Longest clock path from clock "rdclk" to source register is 2.871 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'
        Info: 3: + IC(0.926 ns) + CELL(0.666 ns) = 2.871 ns; Loc. = LCFF_X28_Y18_N25; Fanout = 1; REG Node = 'sync:inst7|addr_s[0]'
        Info: Total cell delay = 1.806 ns ( 62.90 % )
        Info: Total interconnect delay = 1.065 ns ( 37.10 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 11.892 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y18_N25; Fanout = 1; REG Node = 'sync:inst7|addr_s[0]'
        Info: 2: + IC(4.270 ns) + CELL(0.646 ns) = 4.916 ns; Loc. = LCCOMB_X1_Y16_N28; Fanout = 1; COMB Node = 'empty_cmp:inst5|Equal0~132'
        Info: 3: + IC(0.673 ns) + CELL(0.370 ns) = 5.959 ns; Loc. = LCCOMB_X1_Y16_N10; Fanout = 2; COMB Node = 'empty_cmp:inst5|Equal0~134'
        Info: 4: + IC(0.406 ns) + CELL(0.650 ns) = 7.015 ns; Loc. = LCCOMB_X1_Y16_N22; Fanout = 1; COMB Node = 'inst11'
        Info: 5: + IC(1.601 ns) + CELL(3.276 ns) = 11.892 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'rden_vaild'
        Info: Total cell delay = 4.942 ns ( 41.56 % )
        Info: Total interconnect delay = 6.950 ns ( 58.44 % )
Info: Longest tpd from source pin "rd_addr_grey[3]" to destination pin "rden_vaild" is 15.032 ns
    Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_197; Fanout = 2; PIN Node = 'rd_addr_grey[3]'
    Info: 2: + IC(6.508 ns) + CELL(0.623 ns) = 8.105 ns; Loc. = LCCOMB_X1_Y16_N2; Fanout = 3; COMB Node = 'empty_cmp:inst5|Equal0~131'
    Info: 3: + IC(0.378 ns) + CELL(0.616 ns) = 9.099 ns; Loc. = LCCOMB_X1_Y16_N10; Fanout = 2; COMB Node = 'empty_cmp:inst5|Equal0~134'
    Info: 4: + IC(0.406 ns) + CELL(0.650 ns) = 10.155 ns; Loc. = LCCOMB_X1_Y16_N22; Fanout = 1; COMB Node = 'inst11'
    Info: 5: + IC(1.601 ns) + CELL(3.276 ns) = 15.032 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'rden_vaild'
    Info: Total cell delay = 6.139 ns ( 40.84 % )
    Info: Total interconnect delay = 8.893 ns ( 59.16 % )
Info: th for register "sync:inst7|temp[4]" (data pin = "wr_addr_gery[4]", clock pin = "rdclk") is 0.217 ns
    Info: + Longest clock path from clock "rdclk" to destination register is 2.864 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'rdclk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'rdclk~clkctrl'
        Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X1_Y16_N15; Fanout = 1; REG Node = 'sync:inst7|temp[4]'
        Info: Total cell delay = 1.806 ns ( 63.06 % )
        Info: Total interconnect delay = 1.058 ns ( 36.94 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 2.953 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_28; Fanout = 2; PIN Node = 'wr_addr_gery[4]'
        Info: 2: + IC(1.353 ns) + CELL(0.460 ns) = 2.953 ns; Loc. = LCFF_X1_Y16_N15; Fanout = 1; REG Node = 'sync:inst7|temp[4]'
        Info: Total cell delay = 1.600 ns ( 54.18 % )
        Info: Total interconnect delay = 1.353 ns ( 45.82 % )
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 131 megabytes
    Info: Processing ended: Fri Apr 10 20:23:35 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01