sync.map.summary

来自「基于FPGA编写的VHDL语言」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Thu Apr 09 15:31:32 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : sync
Top-level Entity Name : sync
Family : Cyclone II
Total logic elements : 8
    Total combinational functions : 0
    Dedicated logic registers : 8
Total registers : 8
Total pins : 9
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0