g2b.vhd

基于FPGA编写的VHDL语言

--g2b
--
--
library ieee;
use ieee.STD_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity g2b is
 generic(n: integer :=4);
port(
     --
     grey:in std_logic_vector(n-1 downto 0);
     norm:out std_logic_vector(n-1 downto 0)   
);
end g2b;

architecture behave of g2b is
 begin
   process(grey)
     variable normal:std_logic_vector(n-1 downto 0);
     variable tem_q:std_logic_vector(n-1 downto 0);
      begin
         tem_q:=grey;
         normal(n-1):=tem_q(n-1);
        for i in n-2 downto 0 loop
          normal(i):=tem_q(i) xor normal(i+1);
        end loop;
        norm<=normal;
   end process;
end behave;