gray.tan.rpt

基于FPGA编写的VHDL语言

+----------------------------------------------------------------+
; tsu                                                            ;
+-------+--------------+------------+------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To       ; To Clock ;
+-------+--------------+------------+------+----------+----------+
; N/A   ; None         ; 5.365 ns   ; en   ; new_q[3] ; clk      ;
; N/A   ; None         ; 5.365 ns   ; en   ; new_q[2] ; clk      ;
; N/A   ; None         ; 5.364 ns   ; en   ; new_q[4] ; clk      ;
; N/A   ; None         ; 4.478 ns   ; en   ; new_q[0] ; clk      ;
; N/A   ; None         ; 4.476 ns   ; en   ; new_q[1] ; clk      ;
+-------+--------------+------------+------+----------+----------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+----------+------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To   ; From Clock ;
+-------+--------------+------------+----------+------+------------+
; N/A   ; None         ; 8.583 ns   ; new_q[0] ; q[0] ; clk        ;
; N/A   ; None         ; 7.550 ns   ; new_q[1] ; q[1] ; clk        ;
; N/A   ; None         ; 7.408 ns   ; new_q[2] ; q[2] ; clk        ;
; N/A   ; None         ; 7.341 ns   ; new_q[3] ; q[3] ; clk        ;
; N/A   ; None         ; 7.314 ns   ; new_q[4] ; q[4] ; clk        ;
+-------+--------------+------------+----------+------+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -4.210 ns ; en   ; new_q[1] ; clk      ;
; N/A           ; None        ; -4.212 ns ; en   ; new_q[0] ; clk      ;
; N/A           ; None        ; -5.098 ns ; en   ; new_q[4] ; clk      ;
; N/A           ; None        ; -5.099 ns ; en   ; new_q[3] ; clk      ;
; N/A           ; None        ; -5.099 ns ; en   ; new_q[2] ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Thu Apr 09 21:10:09 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off gray -c gray --timing_analysis_only
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "new_q[3]" and destination register "new_q[3]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.325 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q[3]'
            Info: 2: + IC(0.438 ns) + CELL(0.623 ns) = 1.061 ns; Loc. = LCCOMB_X1_Y3_N18; Fanout = 3; COMB Node = 'normal[2]'
            Info: 3: + IC(0.371 ns) + CELL(0.206 ns) = 1.638 ns; Loc. = LCCOMB_X1_Y3_N28; Fanout = 3; COMB Node = 'new_q[4]~826'
            Info: 4: + IC(0.373 ns) + CELL(0.206 ns) = 2.217 ns; Loc. = LCCOMB_X1_Y3_N14; Fanout = 1; COMB Node = 'new_q[3]~828'
            Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.325 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q[3]'
            Info: Total cell delay = 1.143 ns ( 49.16 % )
            Info: Total interconnect delay = 1.182 ns ( 50.84 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.866 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q[3]'
                Info: Total cell delay = 1.806 ns ( 63.01 % )
                Info: Total interconnect delay = 1.060 ns ( 36.99 % )
            Info: - Longest clock path from clock "clk" to source register is 2.866 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q[3]'
                Info: Total cell delay = 1.806 ns ( 63.01 % )
                Info: Total interconnect delay = 1.060 ns ( 36.99 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "new_q[3]" (data pin = "en", clock pin = "clk") is 5.365 ns
    Info: + Longest pin to register delay is 8.271 ns
        Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_46; Fanout = 3; PIN Node = 'en'
        Info: 2: + IC(5.966 ns) + CELL(0.623 ns) = 7.584 ns; Loc. = LCCOMB_X1_Y3_N28; Fanout = 3; COMB Node = 'new_q[4]~826'
        Info: 3: + IC(0.373 ns) + CELL(0.206 ns) = 8.163 ns; Loc. = LCCOMB_X1_Y3_N14; Fanout = 1; COMB Node = 'new_q[3]~828'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.271 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q[3]'
        Info: Total cell delay = 1.932 ns ( 23.36 % )
        Info: Total interconnect delay = 6.339 ns ( 76.64 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.866 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q[3]'
        Info: Total cell delay = 1.806 ns ( 63.01 % )
        Info: Total interconnect delay = 1.060 ns ( 36.99 % )
Info: tco from clock "clk" to destination pin "q[0]" through register "new_q[0]" is 8.583 ns
    Info: + Longest clock path from clock "clk" to source register is 2.866 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N25; Fanout = 4; REG Node = 'new_q[0]'
        Info: Total cell delay = 1.806 ns ( 63.01 % )
        Info: Total interconnect delay = 1.060 ns ( 36.99 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.413 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N25; Fanout = 4; REG Node = 'new_q[0]'
        Info: 2: + IC(2.127 ns) + CELL(3.286 ns) = 5.413 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'q[0]'
        Info: Total cell delay = 3.286 ns ( 60.71 % )
        Info: Total interconnect delay = 2.127 ns ( 39.29 % )
Info: th for register "new_q[1]" (data pin = "en", clock pin = "clk") is -4.210 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.866 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N11; Fanout = 4; REG Node = 'new_q[1]'
        Info: Total cell delay = 1.806 ns ( 63.01 % )
        Info: Total interconnect delay = 1.060 ns ( 36.99 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.382 ns
        Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_46; Fanout = 3; PIN Node = 'en'
        Info: 2: + IC(5.628 ns) + CELL(0.651 ns) = 7.274 ns; Loc. = LCCOMB_X1_Y3_N10; Fanout = 1; COMB Node = 'new_q[1]~825'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.382 ns; Loc. = LCFF_X1_Y3_N11; Fanout = 4; REG Node = 'new_q[1]'
        Info: Total cell delay = 1.754 ns ( 23.76 % )
        Info: Total interconnect delay = 5.628 ns ( 76.24 % )
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 131 megabytes
    Info: Processing ended: Thu Apr 09 21:10:10 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01