sync.tan.rpt

基于FPGA编写的VHDL语言

; N/A   ; None         ; 4.119 ns   ; addr_a[0] ; temp[0] ; clk      ;
; N/A   ; None         ; 4.111 ns   ; addr_a[1] ; temp[1] ; clk      ;
+-------+--------------+------------+-----------+---------+----------+


+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+----------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From           ; To        ; From Clock ;
+-------+--------------+------------+----------------+-----------+------------+
; N/A   ; None         ; 7.467 ns   ; addr_s[0]~reg0 ; addr_s[0] ; clk        ;
; N/A   ; None         ; 7.274 ns   ; addr_s[1]~reg0 ; addr_s[1] ; clk        ;
; N/A   ; None         ; 7.267 ns   ; addr_s[2]~reg0 ; addr_s[2] ; clk        ;
; N/A   ; None         ; 6.980 ns   ; addr_s[3]~reg0 ; addr_s[3] ; clk        ;
+-------+--------------+------------+----------------+-----------+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+-----------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To      ; To Clock ;
+---------------+-------------+-----------+-----------+---------+----------+
; N/A           ; None        ; -3.845 ns ; addr_a[1] ; temp[1] ; clk      ;
; N/A           ; None        ; -3.853 ns ; addr_a[0] ; temp[0] ; clk      ;
; N/A           ; None        ; -3.961 ns ; addr_a[3] ; temp[3] ; clk      ;
; N/A           ; None        ; -4.804 ns ; addr_a[2] ; temp[2] ; clk      ;
+---------------+-------------+-----------+-----------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Thu Apr 09 15:31:40 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sync -c sync --timing_analysis_only
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "temp[1]" and destination register "addr_s[1]~reg0"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.739 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'temp[1]'
            Info: 2: + IC(0.425 ns) + CELL(0.206 ns) = 0.631 ns; Loc. = LCCOMB_X1_Y1_N0; Fanout = 1; COMB Node = 'addr_s[1]~reg0feeder'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.739 ns; Loc. = LCFF_X1_Y1_N1; Fanout = 1; REG Node = 'addr_s[1]~reg0'
            Info: Total cell delay = 0.314 ns ( 42.49 % )
            Info: Total interconnect delay = 0.425 ns ( 57.51 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.868 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.923 ns) + CELL(0.666 ns) = 2.868 ns; Loc. = LCFF_X1_Y1_N1; Fanout = 1; REG Node = 'addr_s[1]~reg0'
                Info: Total cell delay = 1.806 ns ( 62.97 % )
                Info: Total interconnect delay = 1.062 ns ( 37.03 % )
            Info: - Longest clock path from clock "clk" to source register is 2.868 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.923 ns) + CELL(0.666 ns) = 2.868 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'temp[1]'
                Info: Total cell delay = 1.806 ns ( 62.97 % )
                Info: Total interconnect delay = 1.062 ns ( 37.03 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "temp[2]" (data pin = "addr_a[2]", clock pin = "clk") is 5.070 ns
    Info: + Longest pin to register delay is 7.964 ns
        Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'addr_a[2]'
        Info: 2: + IC(6.540 ns) + CELL(0.460 ns) = 7.964 ns; Loc. = LCFF_X30_Y7_N27; Fanout = 1; REG Node = 'temp[2]'
        Info: Total cell delay = 1.424 ns ( 17.88 % )
        Info: Total interconnect delay = 6.540 ns ( 82.12 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.854 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.909 ns) + CELL(0.666 ns) = 2.854 ns; Loc. = LCFF_X30_Y7_N27; Fanout = 1; REG Node = 'temp[2]'
        Info: Total cell delay = 1.806 ns ( 63.28 % )
        Info: Total interconnect delay = 1.048 ns ( 36.72 % )
Info: tco from clock "clk" to destination pin "addr_s[0]" through register "addr_s[0]~reg0" is 7.467 ns
    Info: + Longest clock path from clock "clk" to source register is 2.878 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.933 ns) + CELL(0.666 ns) = 2.878 ns; Loc. = LCFF_X14_Y4_N9; Fanout = 1; REG Node = 'addr_s[0]~reg0'
        Info: Total cell delay = 1.806 ns ( 62.75 % )
        Info: Total interconnect delay = 1.072 ns ( 37.25 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.285 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y4_N9; Fanout = 1; REG Node = 'addr_s[0]~reg0'
        Info: 2: + IC(0.999 ns) + CELL(3.286 ns) = 4.285 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'addr_s[0]'
        Info: Total cell delay = 3.286 ns ( 76.69 % )
        Info: Total interconnect delay = 0.999 ns ( 23.31 % )
Info: th for register "temp[1]" (data pin = "addr_a[1]", clock pin = "clk") is -3.845 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.868 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.923 ns) + CELL(0.666 ns) = 2.868 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'temp[1]'
        Info: Total cell delay = 1.806 ns ( 62.97 % )
        Info: Total interconnect delay = 1.062 ns ( 37.03 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.019 ns
        Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_58; Fanout = 1; PIN Node = 'addr_a[1]'
        Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.911 ns; Loc. = LCCOMB_X1_Y1_N26; Fanout = 1; COMB Node = 'temp[1]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.019 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'temp[1]'
        Info: Total cell delay = 1.318 ns ( 18.78 % )
        Info: Total interconnect delay = 5.701 ns ( 81.22 % )
Info: Parallel compilation was enabled but no parallel operations were performed
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 131 megabytes
    Info: Processing ended: Thu Apr 09 15:31:41 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01