pll_ram_modelsim.xrf

ModelSim对Altera设计进行功能仿真的简单操作步骤

vendor_name = ModelSim
source_file = 1, pllx2.v
source_file = 1, pll_ram.v
source_file = 1, dpram8x32.v
source_file = 1, c:/eda/quartus/libraries/megafunctions/altpll.tdf
source_file = 1, c:/eda/quartus/libraries/megafunctions/aglobal.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/stratix_pll.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/stratixii_pll.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/altsyncram.tdf
source_file = 1, c:/eda/quartus/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/lpm_mux.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/lpm_decode.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/altsyncram.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/a_rdenreg.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/altrom.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/altram.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/altdpram.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/altqpram.inc
source_file = 1, d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf
source_file = 1, c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf
source_file = 1, c:/eda/quartus/libraries/megafunctions/lpm_constant.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/lpm_add_sub.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/cmpconst.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/lpm_compare.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/lpm_counter.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/dffeea.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/alt_synch_counter.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/alt_synch_counter_f.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/alt_counter_f10ke.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.inc
source_file = 1, c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf
source_file = 1, c:/eda/quartus/libraries/megafunctions/stratix_lcell.inc
design_name = pll_ram
instance = net, \pllx2_u1|altpll_component|_clk1 , pllx2_u1|altpll_component|_clk1, pll_ram, 1
instance = net, \pllx2_u1|altpll_component|_clk2 , pllx2_u1|altpll_component|_clk2, pll_ram, 1
instance = net, \pllx2_u1|altpll_component|_clk3 , pllx2_u1|altpll_component|_clk3, pll_ram, 1
instance = net, \pllx2_u1|altpll_component|_clk4 , pllx2_u1|altpll_component|_clk4, pll_ram, 1
instance = net, \pllx2_u1|altpll_component|_clk5 , pllx2_u1|altpll_component|_clk5, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|counter_cell[3]~COUT , wr_addr_rtl_0|wysi_counter|counter_cell[3]~COUT, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|counter_cell[2]~COUT , wr_addr_rtl_0|wysi_counter|counter_cell[2]~COUT, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|counter_cell[1]~COUT , wr_addr_rtl_0|wysi_counter|counter_cell[1]~COUT, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|counter_cell[0]~COUT , wr_addr_rtl_0|wysi_counter|counter_cell[0]~COUT, pll_ram, 1
instance = net, \rst~combout , rst, pll_ram, 1
instance = net, \clk_in~combout , clk_in, pll_ram, 1
instance = net, \pllx2_u1|altpll_component|_clk0 , pllx2_u1|altpll_component|_clk0, pll_ram, 1
instance = net, \pllx2_u1|altpll_component|_locked , pllx2_u1|altpll_component|_locked, pll_ram, 1
instance = net, \wr_en~combout , wr_en, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[0] , wr_addr_rtl_0|wysi_counter|safe_q[0], pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT0 , wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT0, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT1 , wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT1, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[1] , wr_addr_rtl_0|wysi_counter|safe_q[1], pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT0 , wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT0, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT1 , wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT1, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[2] , wr_addr_rtl_0|wysi_counter|safe_q[2], pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT0 , wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT0, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT1 , wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT1, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[3] , wr_addr_rtl_0|wysi_counter|safe_q[3], pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT0 , wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT0, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT1 , wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT1, pll_ram, 1
instance = net, \wr_addr_rtl_0|wysi_counter|safe_q[4] , wr_addr_rtl_0|wysi_counter|safe_q[4], pll_ram, 1
instance = net, \i~24 , i~24, pll_ram, 1
instance = net, \i~1 , i~1, pll_ram, 1
instance = net, \rd_en~combout , rd_en, pll_ram, 1
instance = net, \data_in[0]~combout , data_in[0], pll_ram, 1
instance = net, \rd_addr[0]~combout , rd_addr[0], pll_ram, 1
instance = net, \rd_addr[1]~combout , rd_addr[1], pll_ram, 1
instance = net, \rd_addr[2]~combout , rd_addr[2], pll_ram, 1
instance = net, \rd_addr[3]~combout , rd_addr[3], pll_ram, 1
instance = net, \rd_addr[4]~combout , rd_addr[4], pll_ram, 1
instance = net, \~STRATIX_FITTER_CREATED_GND , ~STRATIX_FITTER_CREATED_GND, pll_ram, 1
instance = net, \data_in[1]~combout , data_in[1], pll_ram, 1
instance = net, \data_in[2]~combout , data_in[2], pll_ram, 1
instance = net, \data_in[3]~combout , data_in[3], pll_ram, 1
instance = net, \data_in[4]~combout , data_in[4], pll_ram, 1
instance = net, \data_in[5]~combout , data_in[5], pll_ram, 1
instance = net, \data_in[6]~combout , data_in[6], pll_ram, 1
instance = net, \data_in[7]~combout , data_in[7], pll_ram, 1
instance = net, \dpram8x32_u1|altsyncram_component|auto_generated|q_b[7] , dpram8x32_u1|altsyncram_component|auto_generated|q_b[7], pll_ram, 1
instance = net, \dpram8x32_u1|altsyncram_component|auto_generated|q_b[6] , dpram8x32_u1|altsyncram_component|auto_generated|q_b[6], pll_ram, 1
instance = net, \dpram8x32_u1|altsyncram_component|auto_generated|q_b[5] , dpram8x32_u1|altsyncram_component|auto_generated|q_b[5], pll_ram, 1
instance = net, \dpram8x32_u1|altsyncram_component|auto_generated|q_b[4] , dpram8x32_u1|altsyncram_component|auto_generated|q_b[4], pll_ram, 1
instance = net, \dpram8x32_u1|altsyncram_component|auto_generated|q_b[3] , dpram8x32_u1|altsyncram_component|auto_generated|q_b[3], pll_ram, 1
instance = net, \dpram8x32_u1|altsyncram_component|auto_generated|q_b[2] , dpram8x32_u1|altsyncram_component|auto_generated|q_b[2], pll_ram, 1
instance = net, \dpram8x32_u1|altsyncram_component|auto_generated|q_b[1] , dpram8x32_u1|altsyncram_component|auto_generated|q_b[1], pll_ram, 1
instance = net, \dpram8x32_u1|altsyncram_component|auto_generated|q_b[0] , dpram8x32_u1|altsyncram_component|auto_generated|q_b[0], pll_ram, 1
instance = comp, \rst~I , rst, pll_ram, 1
instance = comp, \clk_in~I , clk_in, pll_ram, 1
instance = comp, \pllx2_u1|altpll_component|pll , pllx2_u1|altpll_component|pll, pll_ram, 1
instance = comp, \wr_en~I , wr_en, pll_ram, 1
instance = comp, \wr_addr_rtl_0|wysi_counter|counter_cell[0] , wr_addr_rtl_0|wysi_counter|counter_cell[0], pll_ram, 1
instance = comp, \wr_addr_rtl_0|wysi_counter|counter_cell[1] , wr_addr_rtl_0|wysi_counter|counter_cell[1], pll_ram, 1
instance = comp, \wr_addr_rtl_0|wysi_counter|counter_cell[2] , wr_addr_rtl_0|wysi_counter|counter_cell[2], pll_ram, 1
instance = comp, \wr_addr_rtl_0|wysi_counter|counter_cell[3] , wr_addr_rtl_0|wysi_counter|counter_cell[3], pll_ram, 1
instance = comp, \wr_addr_rtl_0|wysi_counter|counter_cell[4] , wr_addr_rtl_0|wysi_counter|counter_cell[4], pll_ram, 1
instance = comp, \i~24_I , i~24, pll_ram, 1
instance = comp, \i~1_I , i~1, pll_ram, 1
instance = comp, \rd_en~I , rd_en, pll_ram, 1
instance = comp, \data_in[0]~I , data_in[0], pll_ram, 1
instance = comp, \rd_addr[0]~I , rd_addr[0], pll_ram, 1
instance = comp, \rd_addr[1]~I , rd_addr[1], pll_ram, 1
instance = comp, \rd_addr[2]~I , rd_addr[2], pll_ram, 1
instance = comp, \rd_addr[3]~I , rd_addr[3], pll_ram, 1
instance = comp, \rd_addr[4]~I , rd_addr[4], pll_ram, 1
instance = comp, \~STRATIX_FITTER_CREATED_GND~I , ~STRATIX_FITTER_CREATED_GND~I, pll_ram, 1
instance = comp, \data_in[1]~I , data_in[1], pll_ram, 1
instance = comp, \data_in[2]~I , data_in[2], pll_ram, 1
instance = comp, \data_in[3]~I , data_in[3], pll_ram, 1
instance = comp, \data_in[4]~I , data_in[4], pll_ram, 1
instance = comp, \data_in[5]~I , data_in[5], pll_ram, 1
instance = comp, \data_in[6]~I , data_in[6], pll_ram, 1
instance = comp, \data_in[7]~I , data_in[7], pll_ram, 1
instance = comp, \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 , dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0, pll_ram, 1
instance = comp, \clk_out~I , clk_out, pll_ram, 1
instance = comp, \lock~I , lock, pll_ram, 1
instance = comp, \package_full~I , package_full, pll_ram, 1
instance = comp, \data_out[7]~I , data_out[7], pll_ram, 1
instance = comp, \data_out[6]~I , data_out[6], pll_ram, 1
instance = comp, \data_out[5]~I , data_out[5], pll_ram, 1
instance = comp, \data_out[4]~I , data_out[4], pll_ram, 1
instance = comp, \data_out[3]~I , data_out[3], pll_ram, 1
instance = comp, \data_out[2]~I , data_out[2], pll_ram, 1
instance = comp, \data_out[1]~I , data_out[1], pll_ram, 1
instance = comp, \data_out[0]~I , data_out[0], pll_ram, 1