pll_ram.vo

ModelSim对Altera设计进行功能仿真的简单操作步骤

// synopsys translate_on

// atom is at Pin_E21
stratix_io \package_full~I (
	.datain(!\i~1 ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(package_full),
	.dqsundelayedout());
// synopsys translate_off
defparam \package_full~I .operation_mode = "output";
defparam \package_full~I .ddio_mode = "none";
defparam \package_full~I .input_register_mode = "none";
defparam \package_full~I .output_register_mode = "none";
defparam \package_full~I .oe_register_mode = "none";
defparam \package_full~I .input_async_reset = "none";
defparam \package_full~I .output_async_reset = "none";
defparam \package_full~I .oe_async_reset = "none";
defparam \package_full~I .input_sync_reset = "none";
defparam \package_full~I .output_sync_reset = "none";
defparam \package_full~I .oe_sync_reset = "none";
defparam \package_full~I .input_power_up = "low";
defparam \package_full~I .output_power_up = "low";
defparam \package_full~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_C15
stratix_io \data_out[7]~I (
	.datain(\dpram8x32_u1|altsyncram_component|auto_generated|q_b[7] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(data_out[7]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_out[7]~I .operation_mode = "output";
defparam \data_out[7]~I .ddio_mode = "none";
defparam \data_out[7]~I .input_register_mode = "none";
defparam \data_out[7]~I .output_register_mode = "none";
defparam \data_out[7]~I .oe_register_mode = "none";
defparam \data_out[7]~I .input_async_reset = "none";
defparam \data_out[7]~I .output_async_reset = "none";
defparam \data_out[7]~I .oe_async_reset = "none";
defparam \data_out[7]~I .input_sync_reset = "none";
defparam \data_out[7]~I .output_sync_reset = "none";
defparam \data_out[7]~I .oe_sync_reset = "none";
defparam \data_out[7]~I .input_power_up = "low";
defparam \data_out[7]~I .output_power_up = "low";
defparam \data_out[7]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_B18
stratix_io \data_out[6]~I (
	.datain(\dpram8x32_u1|altsyncram_component|auto_generated|q_b[6] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(data_out[6]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_out[6]~I .operation_mode = "output";
defparam \data_out[6]~I .ddio_mode = "none";
defparam \data_out[6]~I .input_register_mode = "none";
defparam \data_out[6]~I .output_register_mode = "none";
defparam \data_out[6]~I .oe_register_mode = "none";
defparam \data_out[6]~I .input_async_reset = "none";
defparam \data_out[6]~I .output_async_reset = "none";
defparam \data_out[6]~I .oe_async_reset = "none";
defparam \data_out[6]~I .input_sync_reset = "none";
defparam \data_out[6]~I .output_sync_reset = "none";
defparam \data_out[6]~I .oe_sync_reset = "none";
defparam \data_out[6]~I .input_power_up = "low";
defparam \data_out[6]~I .output_power_up = "low";
defparam \data_out[6]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_G19
stratix_io \data_out[5]~I (
	.datain(\dpram8x32_u1|altsyncram_component|auto_generated|q_b[5] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(data_out[5]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_out[5]~I .operation_mode = "output";
defparam \data_out[5]~I .ddio_mode = "none";
defparam \data_out[5]~I .input_register_mode = "none";
defparam \data_out[5]~I .output_register_mode = "none";
defparam \data_out[5]~I .oe_register_mode = "none";
defparam \data_out[5]~I .input_async_reset = "none";
defparam \data_out[5]~I .output_async_reset = "none";
defparam \data_out[5]~I .oe_async_reset = "none";
defparam \data_out[5]~I .input_sync_reset = "none";
defparam \data_out[5]~I .output_sync_reset = "none";
defparam \data_out[5]~I .oe_sync_reset = "none";
defparam \data_out[5]~I .input_power_up = "low";
defparam \data_out[5]~I .output_power_up = "low";
defparam \data_out[5]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_C17
stratix_io \data_out[4]~I (
	.datain(\dpram8x32_u1|altsyncram_component|auto_generated|q_b[4] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(data_out[4]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_out[4]~I .operation_mode = "output";
defparam \data_out[4]~I .ddio_mode = "none";
defparam \data_out[4]~I .input_register_mode = "none";
defparam \data_out[4]~I .output_register_mode = "none";
defparam \data_out[4]~I .oe_register_mode = "none";
defparam \data_out[4]~I .input_async_reset = "none";
defparam \data_out[4]~I .output_async_reset = "none";
defparam \data_out[4]~I .oe_async_reset = "none";
defparam \data_out[4]~I .input_sync_reset = "none";
defparam \data_out[4]~I .output_sync_reset = "none";
defparam \data_out[4]~I .oe_sync_reset = "none";
defparam \data_out[4]~I .input_power_up = "low";
defparam \data_out[4]~I .output_power_up = "low";
defparam \data_out[4]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_D16
stratix_io \data_out[3]~I (
	.datain(\dpram8x32_u1|altsyncram_component|auto_generated|q_b[3] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(data_out[3]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_out[3]~I .operation_mode = "output";
defparam \data_out[3]~I .ddio_mode = "none";
defparam \data_out[3]~I .input_register_mode = "none";
defparam \data_out[3]~I .output_register_mode = "none";
defparam \data_out[3]~I .oe_register_mode = "none";
defparam \data_out[3]~I .input_async_reset = "none";
defparam \data_out[3]~I .output_async_reset = "none";
defparam \data_out[3]~I .oe_async_reset = "none";
defparam \data_out[3]~I .input_sync_reset = "none";
defparam \data_out[3]~I .output_sync_reset = "none";
defparam \data_out[3]~I .oe_sync_reset = "none";
defparam \data_out[3]~I .input_power_up = "low";
defparam \data_out[3]~I .output_power_up = "low";
defparam \data_out[3]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_C16
stratix_io \data_out[2]~I (
	.datain(\dpram8x32_u1|altsyncram_component|auto_generated|q_b[2] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(data_out[2]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_out[2]~I .operation_mode = "output";
defparam \data_out[2]~I .ddio_mode = "none";
defparam \data_out[2]~I .input_register_mode = "none";
defparam \data_out[2]~I .output_register_mode = "none";
defparam \data_out[2]~I .oe_register_mode = "none";
defparam \data_out[2]~I .input_async_reset = "none";
defparam \data_out[2]~I .output_async_reset = "none";
defparam \data_out[2]~I .oe_async_reset = "none";
defparam \data_out[2]~I .input_sync_reset = "none";
defparam \data_out[2]~I .output_sync_reset = "none";
defparam \data_out[2]~I .oe_sync_reset = "none";
defparam \data_out[2]~I .input_power_up = "low";
defparam \data_out[2]~I .output_power_up = "low";
defparam \data_out[2]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_A19
stratix_io \data_out[1]~I (
	.datain(\dpram8x32_u1|altsyncram_component|auto_generated|q_b[1] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(data_out[1]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_out[1]~I .operation_mode = "output";
defparam \data_out[1]~I .ddio_mode = "none";
defparam \data_out[1]~I .input_register_mode = "none";
defparam \data_out[1]~I .output_register_mode = "none";
defparam \data_out[1]~I .oe_register_mode = "none";
defparam \data_out[1]~I .input_async_reset = "none";
defparam \data_out[1]~I .output_async_reset = "none";
defparam \data_out[1]~I .oe_async_reset = "none";
defparam \data_out[1]~I .input_sync_reset = "none";
defparam \data_out[1]~I .output_sync_reset = "none";
defparam \data_out[1]~I .oe_sync_reset = "none";
defparam \data_out[1]~I .input_power_up = "low";
defparam \data_out[1]~I .output_power_up = "low";
defparam \data_out[1]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_F15
stratix_io \data_out[0]~I (
	.datain(\dpram8x32_u1|altsyncram_component|auto_generated|q_b[0] ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(data_out[0]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_out[0]~I .operation_mode = "output";
defparam \data_out[0]~I .ddio_mode = "none";
defparam \data_out[0]~I .input_register_mode = "none";
defparam \data_out[0]~I .output_register_mode = "none";
defparam \data_out[0]~I .oe_register_mode = "none";
defparam \data_out[0]~I .input_async_reset = "none";
defparam \data_out[0]~I .output_async_reset = "none";
defparam \data_out[0]~I .oe_async_reset = "none";
defparam \data_out[0]~I .input_sync_reset = "none";
defparam \data_out[0]~I .output_sync_reset = "none";
defparam \data_out[0]~I .oe_sync_reset = "none";
defparam \data_out[0]~I .input_power_up = "low";
defparam \data_out[0]~I .output_power_up = "low";
defparam \data_out[0]~I .oe_power_up = "low";
// synopsys translate_on

endmodule