pll_ram.vo

ModelSim对Altera设计进行功能仿真的简单操作步骤

	.combout(\data_in[2]~combout ),
	.regout(),
	.ddioregout(),
	.padio(data_in[2]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_in[2]~I .operation_mode = "input";
defparam \data_in[2]~I .ddio_mode = "none";
defparam \data_in[2]~I .input_register_mode = "none";
defparam \data_in[2]~I .output_register_mode = "none";
defparam \data_in[2]~I .oe_register_mode = "none";
defparam \data_in[2]~I .input_async_reset = "none";
defparam \data_in[2]~I .output_async_reset = "none";
defparam \data_in[2]~I .oe_async_reset = "none";
defparam \data_in[2]~I .input_sync_reset = "none";
defparam \data_in[2]~I .output_sync_reset = "none";
defparam \data_in[2]~I .oe_sync_reset = "none";
defparam \data_in[2]~I .input_power_up = "low";
defparam \data_in[2]~I .output_power_up = "low";
defparam \data_in[2]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_H18
stratix_io \data_in[3]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_in[3]~combout ),
	.regout(),
	.ddioregout(),
	.padio(data_in[3]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_in[3]~I .operation_mode = "input";
defparam \data_in[3]~I .ddio_mode = "none";
defparam \data_in[3]~I .input_register_mode = "none";
defparam \data_in[3]~I .output_register_mode = "none";
defparam \data_in[3]~I .oe_register_mode = "none";
defparam \data_in[3]~I .input_async_reset = "none";
defparam \data_in[3]~I .output_async_reset = "none";
defparam \data_in[3]~I .oe_async_reset = "none";
defparam \data_in[3]~I .input_sync_reset = "none";
defparam \data_in[3]~I .output_sync_reset = "none";
defparam \data_in[3]~I .oe_sync_reset = "none";
defparam \data_in[3]~I .input_power_up = "low";
defparam \data_in[3]~I .output_power_up = "low";
defparam \data_in[3]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_F17
stratix_io \data_in[4]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_in[4]~combout ),
	.regout(),
	.ddioregout(),
	.padio(data_in[4]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_in[4]~I .operation_mode = "input";
defparam \data_in[4]~I .ddio_mode = "none";
defparam \data_in[4]~I .input_register_mode = "none";
defparam \data_in[4]~I .output_register_mode = "none";
defparam \data_in[4]~I .oe_register_mode = "none";
defparam \data_in[4]~I .input_async_reset = "none";
defparam \data_in[4]~I .output_async_reset = "none";
defparam \data_in[4]~I .oe_async_reset = "none";
defparam \data_in[4]~I .input_sync_reset = "none";
defparam \data_in[4]~I .output_sync_reset = "none";
defparam \data_in[4]~I .oe_sync_reset = "none";
defparam \data_in[4]~I .input_power_up = "low";
defparam \data_in[4]~I .output_power_up = "low";
defparam \data_in[4]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_G18
stratix_io \data_in[5]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_in[5]~combout ),
	.regout(),
	.ddioregout(),
	.padio(data_in[5]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_in[5]~I .operation_mode = "input";
defparam \data_in[5]~I .ddio_mode = "none";
defparam \data_in[5]~I .input_register_mode = "none";
defparam \data_in[5]~I .output_register_mode = "none";
defparam \data_in[5]~I .oe_register_mode = "none";
defparam \data_in[5]~I .input_async_reset = "none";
defparam \data_in[5]~I .output_async_reset = "none";
defparam \data_in[5]~I .oe_async_reset = "none";
defparam \data_in[5]~I .input_sync_reset = "none";
defparam \data_in[5]~I .output_sync_reset = "none";
defparam \data_in[5]~I .oe_sync_reset = "none";
defparam \data_in[5]~I .input_power_up = "low";
defparam \data_in[5]~I .output_power_up = "low";
defparam \data_in[5]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_E16
stratix_io \data_in[6]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_in[6]~combout ),
	.regout(),
	.ddioregout(),
	.padio(data_in[6]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_in[6]~I .operation_mode = "input";
defparam \data_in[6]~I .ddio_mode = "none";
defparam \data_in[6]~I .input_register_mode = "none";
defparam \data_in[6]~I .output_register_mode = "none";
defparam \data_in[6]~I .oe_register_mode = "none";
defparam \data_in[6]~I .input_async_reset = "none";
defparam \data_in[6]~I .output_async_reset = "none";
defparam \data_in[6]~I .oe_async_reset = "none";
defparam \data_in[6]~I .input_sync_reset = "none";
defparam \data_in[6]~I .output_sync_reset = "none";
defparam \data_in[6]~I .oe_sync_reset = "none";
defparam \data_in[6]~I .input_power_up = "low";
defparam \data_in[6]~I .output_power_up = "low";
defparam \data_in[6]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_E17
stratix_io \data_in[7]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_in[7]~combout ),
	.regout(),
	.ddioregout(),
	.padio(data_in[7]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_in[7]~I .operation_mode = "input";
defparam \data_in[7]~I .ddio_mode = "none";
defparam \data_in[7]~I .input_register_mode = "none";
defparam \data_in[7]~I .output_register_mode = "none";
defparam \data_in[7]~I .oe_register_mode = "none";
defparam \data_in[7]~I .input_async_reset = "none";
defparam \data_in[7]~I .output_async_reset = "none";
defparam \data_in[7]~I .oe_async_reset = "none";
defparam \data_in[7]~I .input_sync_reset = "none";
defparam \data_in[7]~I .output_sync_reset = "none";
defparam \data_in[7]~I .oe_sync_reset = "none";
defparam \data_in[7]~I .input_power_up = "low";
defparam \data_in[7]~I .output_power_up = "low";
defparam \data_in[7]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at M4K_X37_Y29
stratix_ram_block \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 (
	.portawe(\wr_en~combout ),
	.portbrewe(\rd_en~combout ),
	.clk0(\pllx2_u1|altpll_component|_clk0 ),
	.clk1(),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(!\rst~combout ),
	.clr1(gnd),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\data_in[7]~combout ,\data_in[6]~combout ,\data_in[5]~combout ,\data_in[4]~combout ,\data_in[3]~combout ,
\data_in[2]~combout ,\data_in[1]~combout ,\data_in[0]~combout }),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\wr_addr_rtl_0|wysi_counter|safe_q[4] ,\wr_addr_rtl_0|wysi_counter|safe_q[3] ,\wr_addr_rtl_0|wysi_counter|safe_q[2] ,\wr_addr_rtl_0|wysi_counter|safe_q[1] ,\wr_addr_rtl_0|wysi_counter|safe_q[0] }),
	.portabyteenamasks(),
	.portbdatain(),
	.portbaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\rd_addr[4]~combout ,\rd_addr[3]~combout ,\rd_addr[2]~combout ,\rd_addr[1]~combout ,\rd_addr[0]~combout }),
	.portbbyteenamasks(),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout ));
// synopsys translate_off
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "dual_port";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M4K";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ALTSYNCRAM";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 5;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 5;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_in_clear = "clear0";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "clear0";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clear = "clear0";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 31;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 8;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 32;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock0";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "clear0";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock0";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "clear0";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock0";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "clear0";
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 31;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
defparam \dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 8;
// synopsys translate_on

// atom is at Pin_P8
stratix_io \clk_out~I (
	.datain(\pllx2_u1|altpll_component|_clk0 ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(clk_out),
	.dqsundelayedout());
// synopsys translate_off
defparam \clk_out~I .operation_mode = "output";
defparam \clk_out~I .ddio_mode = "none";
defparam \clk_out~I .input_register_mode = "none";
defparam \clk_out~I .output_register_mode = "none";
defparam \clk_out~I .oe_register_mode = "none";
defparam \clk_out~I .input_async_reset = "none";
defparam \clk_out~I .output_async_reset = "none";
defparam \clk_out~I .oe_async_reset = "none";
defparam \clk_out~I .input_sync_reset = "none";
defparam \clk_out~I .output_sync_reset = "none";
defparam \clk_out~I .oe_sync_reset = "none";
defparam \clk_out~I .input_power_up = "low";
defparam \clk_out~I .output_power_up = "low";
defparam \clk_out~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_F14
stratix_io \lock~I (
	.datain(\pllx2_u1|altpll_component|_locked ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(lock),
	.dqsundelayedout());
// synopsys translate_off
defparam \lock~I .operation_mode = "output";
defparam \lock~I .ddio_mode = "none";
defparam \lock~I .input_register_mode = "none";
defparam \lock~I .output_register_mode = "none";
defparam \lock~I .oe_register_mode = "none";
defparam \lock~I .input_async_reset = "none";
defparam \lock~I .output_async_reset = "none";
defparam \lock~I .oe_async_reset = "none";
defparam \lock~I .input_sync_reset = "none";
defparam \lock~I .output_sync_reset = "none";
defparam \lock~I .oe_sync_reset = "none";
defparam \lock~I .input_power_up = "low";
defparam \lock~I .output_power_up = "low";
defparam \lock~I .oe_power_up = "low";