pll_ram.vo

ModelSim对Altera设计进行功能仿真的简单操作步骤

defparam \pllx2_u1|altpll_component|pll .extclk1_phase_shift = "0";
defparam \pllx2_u1|altpll_component|pll .extclk2_phase_shift = "0";
defparam \pllx2_u1|altpll_component|pll .extclk3_phase_shift = "0";
defparam \pllx2_u1|altpll_component|pll .clk0_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .clk1_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .clk2_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .clk3_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .clk4_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .clk5_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .extclk0_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .extclk1_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .extclk2_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .extclk3_time_delay = "0";
defparam \pllx2_u1|altpll_component|pll .clk0_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .clk1_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .clk2_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .clk3_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .clk4_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .clk5_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .extclk0_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .extclk1_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .extclk2_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .extclk3_duty_cycle = 50;
defparam \pllx2_u1|altpll_component|pll .simulation_type = "timing";
// synopsys translate_on

// atom is at Pin_F19
stratix_io \wr_en~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\wr_en~combout ),
	.regout(),
	.ddioregout(),
	.padio(wr_en),
	.dqsundelayedout());
// synopsys translate_off
defparam \wr_en~I .operation_mode = "input";
defparam \wr_en~I .ddio_mode = "none";
defparam \wr_en~I .input_register_mode = "none";
defparam \wr_en~I .output_register_mode = "none";
defparam \wr_en~I .oe_register_mode = "none";
defparam \wr_en~I .input_async_reset = "none";
defparam \wr_en~I .output_async_reset = "none";
defparam \wr_en~I .oe_async_reset = "none";
defparam \wr_en~I .input_sync_reset = "none";
defparam \wr_en~I .output_sync_reset = "none";
defparam \wr_en~I .oe_sync_reset = "none";
defparam \wr_en~I .input_power_up = "low";
defparam \wr_en~I .output_power_up = "low";
defparam \wr_en~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X39_Y29_N5
stratix_lcell \wr_addr_rtl_0|wysi_counter|counter_cell[0] (
// Equation(s):
// \wr_addr_rtl_0|wysi_counter|safe_q[0]  = DFFEA(\wr_en~combout  $ \wr_addr_rtl_0|wysi_counter|safe_q[0] , GLOBAL(\pllx2_u1|altpll_component|_clk0 ), GLOBAL(\rst~combout ), , , , )
// \wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT0  = CARRY(\wr_addr_rtl_0|wysi_counter|safe_q[0] )
// \wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT1  = CARRY(\wr_addr_rtl_0|wysi_counter|safe_q[0] )

	.clk(\pllx2_u1|altpll_component|_clk0 ),
	.dataa(\wr_en~combout ),
	.datab(\wr_addr_rtl_0|wysi_counter|safe_q[0] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\wr_addr_rtl_0|wysi_counter|safe_q[0] ),
	.cout(),
	.cout0(\wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT0 ),
	.cout1(\wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT1 ));
// synopsys translate_off
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[0] .operation_mode = "arithmetic";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[0] .synch_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[0] .register_cascade_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[0] .sum_lutc_input = "datac";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[0] .lut_mask = "66CC";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[0] .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X39_Y29_N6
stratix_lcell \wr_addr_rtl_0|wysi_counter|counter_cell[1] (
// Equation(s):
// \wr_addr_rtl_0|wysi_counter|safe_q[1]  = DFFEA(\wr_addr_rtl_0|wysi_counter|safe_q[1]  $ (\wr_en~combout  & \wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT0 ), GLOBAL(\pllx2_u1|altpll_component|_clk0 ), GLOBAL(\rst~combout ), , , , )
// \wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT0  = CARRY(!\wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT0  # !\wr_addr_rtl_0|wysi_counter|safe_q[1] )
// \wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT1  = CARRY(!\wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT1  # !\wr_addr_rtl_0|wysi_counter|safe_q[1] )

	.clk(\pllx2_u1|altpll_component|_clk0 ),
	.dataa(\wr_addr_rtl_0|wysi_counter|safe_q[1] ),
	.datab(\wr_en~combout ),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT0 ),
	.cin1(\wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT1 ),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\wr_addr_rtl_0|wysi_counter|safe_q[1] ),
	.cout(),
	.cout0(\wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT0 ),
	.cout1(\wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT1 ));
// synopsys translate_off
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[1] .operation_mode = "arithmetic";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[1] .synch_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[1] .register_cascade_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[1] .sum_lutc_input = "cin";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[1] .lut_mask = "6A5F";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[1] .cin0_used = "true";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[1] .cin1_used = "true";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[1] .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X39_Y29_N7
stratix_lcell \wr_addr_rtl_0|wysi_counter|counter_cell[2] (
// Equation(s):
// \wr_addr_rtl_0|wysi_counter|safe_q[2]  = DFFEA(\wr_addr_rtl_0|wysi_counter|safe_q[2]  $ (\wr_en~combout  & !\wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT0 ), GLOBAL(\pllx2_u1|altpll_component|_clk0 ), GLOBAL(\rst~combout ), , , , )
// \wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT0  = CARRY(\wr_addr_rtl_0|wysi_counter|safe_q[2]  & !\wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT0 )
// \wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT1  = CARRY(\wr_addr_rtl_0|wysi_counter|safe_q[2]  & !\wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT1 )

	.clk(\pllx2_u1|altpll_component|_clk0 ),
	.dataa(\wr_addr_rtl_0|wysi_counter|safe_q[2] ),
	.datab(\wr_en~combout ),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT0 ),
	.cin1(\wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT1 ),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\wr_addr_rtl_0|wysi_counter|safe_q[2] ),
	.cout(),
	.cout0(\wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT0 ),
	.cout1(\wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT1 ));
// synopsys translate_off
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[2] .operation_mode = "arithmetic";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[2] .synch_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[2] .register_cascade_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[2] .sum_lutc_input = "cin";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[2] .lut_mask = "A60A";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[2] .cin0_used = "true";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[2] .cin1_used = "true";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[2] .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X39_Y29_N8
stratix_lcell \wr_addr_rtl_0|wysi_counter|counter_cell[3] (
// Equation(s):
// \wr_addr_rtl_0|wysi_counter|safe_q[3]  = DFFEA(\wr_addr_rtl_0|wysi_counter|safe_q[3]  $ (\wr_en~combout  & \wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT0 ), GLOBAL(\pllx2_u1|altpll_component|_clk0 ), GLOBAL(\rst~combout ), , , , )
// \wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT0  = CARRY(!\wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT0  # !\wr_addr_rtl_0|wysi_counter|safe_q[3] )
// \wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT1  = CARRY(!\wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT1  # !\wr_addr_rtl_0|wysi_counter|safe_q[3] )

	.clk(\pllx2_u1|altpll_component|_clk0 ),
	.dataa(\wr_addr_rtl_0|wysi_counter|safe_q[3] ),
	.datab(\wr_en~combout ),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT0 ),
	.cin1(\wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT1 ),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\wr_addr_rtl_0|wysi_counter|safe_q[3] ),
	.cout(),
	.cout0(\wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT0 ),
	.cout1(\wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT1 ));
// synopsys translate_off
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[3] .operation_mode = "arithmetic";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[3] .synch_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[3] .register_cascade_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[3] .sum_lutc_input = "cin";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[3] .lut_mask = "6A5F";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[3] .cin0_used = "true";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[3] .cin1_used = "true";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[3] .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X39_Y29_N9
stratix_lcell \wr_addr_rtl_0|wysi_counter|counter_cell[4] (
// Equation(s):
// \wr_addr_rtl_0|wysi_counter|safe_q[4]  = DFFEA(\wr_addr_rtl_0|wysi_counter|safe_q[4]  $ (\wr_en~combout  & !\wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT0 ), GLOBAL(\pllx2_u1|altpll_component|_clk0 ), GLOBAL(\rst~combout ), , , , )

	.clk(\pllx2_u1|altpll_component|_clk0 ),
	.dataa(vcc),
	.datab(\wr_en~combout ),
	.datac(vcc),
	.datad(\wr_addr_rtl_0|wysi_counter|safe_q[4] ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT0 ),
	.cin1(\wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT1 ),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\wr_addr_rtl_0|wysi_counter|safe_q[4] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[4] .operation_mode = "normal";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[4] .synch_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[4] .register_cascade_mode = "off";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[4] .sum_lutc_input = "cin";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[4] .lut_mask = "F30C";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[4] .cin0_used = "true";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[4] .cin1_used = "true";
defparam \wr_addr_rtl_0|wysi_counter|counter_cell[4] .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X39_Y29_N4
stratix_lcell \i~24_I (
// Equation(s):
// \i~24  = !\wr_addr_rtl_0|wysi_counter|safe_q[3]  # !\wr_addr_rtl_0|wysi_counter|safe_q[2]  # !\wr_addr_rtl_0|wysi_counter|safe_q[4]  # !\wr_addr_rtl_0|wysi_counter|safe_q[1] 

	.clk(),
	.dataa(\wr_addr_rtl_0|wysi_counter|safe_q[1] ),
	.datab(\wr_addr_rtl_0|wysi_counter|safe_q[4] ),
	.datac(\wr_addr_rtl_0|wysi_counter|safe_q[2] ),
	.datad(\wr_addr_rtl_0|wysi_counter|safe_q[3] ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i~24 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \i~24_I .operation_mode = "normal";
defparam \i~24_I .synch_mode = "off";
defparam \i~24_I .register_cascade_mode = "off";
defparam \i~24_I .sum_lutc_input = "datac";
defparam \i~24_I .lut_mask = "7FFF";
defparam \i~24_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X39_Y29_N3
stratix_lcell \i~1_I (
// Equation(s):
// \i~1  = \i~24  # !\wr_addr_rtl_0|wysi_counter|safe_q[0] 

	.clk(),
	.dataa(vcc),
	.datab(vcc),
	.datac(\wr_addr_rtl_0|wysi_counter|safe_q[0] ),
	.datad(\i~24 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i~1 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \i~1_I .operation_mode = "normal";
defparam \i~1_I .synch_mode = "off";
defparam \i~1_I .register_cascade_mode = "off";
defparam \i~1_I .sum_lutc_input = "datac";
defparam \i~1_I .lut_mask = "FF0F";
defparam \i~1_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at Pin_B17
stratix_io \rd_en~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),