pll_ram.vo

ModelSim对Altera设计进行功能仿真的简单操作步骤

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.0 Build 190 1/28/2004 SJ Full Version"

// DATE "12/05/2004 05:43:10"

// 
// Device: Altera EP1S10B672C6 Package BGA672
// 

// 
// This Verilog file should be used for ModelSim (Verilog HDL output from Quartus II) only
// 

`timescale 1 ps/ 1 ps

module 	pll_ram (
	rst,
	clk_in,
	wr_en,
	rd_en,
	data_in,
	rd_addr,
	clk_out,
	lock,
	package_full,
	data_out);
input 	rst;
input 	clk_in;
input 	wr_en;
input 	rd_en;
input 	[7:0] data_in;
input 	[4:0] rd_addr;
output 	clk_out;
output 	lock;
output 	package_full;
output 	[7:0] data_out;

supply0 gnd;
supply1 vcc;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("pll_ram_v.sdo");
// synopsys translate_on

wire \pllx2_u1|altpll_component|_clk1 ;
wire \pllx2_u1|altpll_component|_clk2 ;
wire \pllx2_u1|altpll_component|_clk3 ;
wire \pllx2_u1|altpll_component|_clk4 ;
wire \pllx2_u1|altpll_component|_clk5 ;
wire \wr_addr_rtl_0|wysi_counter|counter_cell[3]~COUT ;
wire \wr_addr_rtl_0|wysi_counter|counter_cell[2]~COUT ;
wire \wr_addr_rtl_0|wysi_counter|counter_cell[1]~COUT ;
wire \wr_addr_rtl_0|wysi_counter|counter_cell[0]~COUT ;
wire \rst~combout ;
wire \clk_in~combout ;
wire \pllx2_u1|altpll_component|_clk0 ;
wire \pllx2_u1|altpll_component|_locked ;
wire \wr_en~combout ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[0] ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT0 ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[0]~COUT1 ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[1] ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT0 ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[1]~COUT1 ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[2] ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT0 ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[2]~COUT1 ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[3] ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT0 ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[3]~COUT1 ;
wire \wr_addr_rtl_0|wysi_counter|safe_q[4] ;
wire \i~24 ;
wire \i~1 ;
wire \rd_en~combout ;
wire \data_in[0]~combout ;
wire \rd_addr[0]~combout ;
wire \rd_addr[1]~combout ;
wire \rd_addr[2]~combout ;
wire \rd_addr[3]~combout ;
wire \rd_addr[4]~combout ;
wire \~STRATIX_FITTER_CREATED_GND ;
wire \data_in[1]~combout ;
wire \data_in[2]~combout ;
wire \data_in[3]~combout ;
wire \data_in[4]~combout ;
wire \data_in[5]~combout ;
wire \data_in[6]~combout ;
wire \data_in[7]~combout ;
wire \dpram8x32_u1|altsyncram_component|auto_generated|q_b[7] ;
wire \dpram8x32_u1|altsyncram_component|auto_generated|q_b[6] ;
wire \dpram8x32_u1|altsyncram_component|auto_generated|q_b[5] ;
wire \dpram8x32_u1|altsyncram_component|auto_generated|q_b[4] ;
wire \dpram8x32_u1|altsyncram_component|auto_generated|q_b[3] ;
wire \dpram8x32_u1|altsyncram_component|auto_generated|q_b[2] ;
wire \dpram8x32_u1|altsyncram_component|auto_generated|q_b[1] ;
wire \dpram8x32_u1|altsyncram_component|auto_generated|q_b[0] ;

wire [5:0] \ww_pllx2_u1|altpll_component|pll_clk ;
wire [143:0] \ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout ;

assign \pllx2_u1|altpll_component|_clk0  = \ww_pllx2_u1|altpll_component|pll_clk [0];
assign \pllx2_u1|altpll_component|_clk1  = \ww_pllx2_u1|altpll_component|pll_clk [1];
assign \pllx2_u1|altpll_component|_clk2  = \ww_pllx2_u1|altpll_component|pll_clk [2];
assign \pllx2_u1|altpll_component|_clk3  = \ww_pllx2_u1|altpll_component|pll_clk [3];
assign \pllx2_u1|altpll_component|_clk4  = \ww_pllx2_u1|altpll_component|pll_clk [4];
assign \pllx2_u1|altpll_component|_clk5  = \ww_pllx2_u1|altpll_component|pll_clk [5];

assign \dpram8x32_u1|altsyncram_component|auto_generated|q_b[0]  = \ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout [0];
assign \dpram8x32_u1|altsyncram_component|auto_generated|q_b[1]  = \ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout [1];
assign \dpram8x32_u1|altsyncram_component|auto_generated|q_b[2]  = \ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout [2];
assign \dpram8x32_u1|altsyncram_component|auto_generated|q_b[3]  = \ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout [3];
assign \dpram8x32_u1|altsyncram_component|auto_generated|q_b[4]  = \ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout [4];
assign \dpram8x32_u1|altsyncram_component|auto_generated|q_b[5]  = \ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout [5];
assign \dpram8x32_u1|altsyncram_component|auto_generated|q_b[6]  = \ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout [6];
assign \dpram8x32_u1|altsyncram_component|auto_generated|q_b[7]  = \ww_dpram8x32_u1|altsyncram_component|auto_generated|ram_block1a0_bdataout [7];

// atom is at Pin_M24
stratix_io \rst~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rst~combout ),
	.regout(),
	.ddioregout(),
	.padio(rst),
	.dqsundelayedout());
// synopsys translate_off
defparam \rst~I .operation_mode = "input";
defparam \rst~I .ddio_mode = "none";
defparam \rst~I .input_register_mode = "none";
defparam \rst~I .output_register_mode = "none";
defparam \rst~I .oe_register_mode = "none";
defparam \rst~I .input_async_reset = "none";
defparam \rst~I .output_async_reset = "none";
defparam \rst~I .oe_async_reset = "none";
defparam \rst~I .input_sync_reset = "none";
defparam \rst~I .output_sync_reset = "none";
defparam \rst~I .oe_sync_reset = "none";
defparam \rst~I .input_power_up = "low";
defparam \rst~I .output_power_up = "low";
defparam \rst~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_B12
stratix_io \clk_in~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk_in~combout ),
	.regout(),
	.ddioregout(),
	.padio(clk_in),
	.dqsundelayedout());
// synopsys translate_off
defparam \clk_in~I .operation_mode = "input";
defparam \clk_in~I .ddio_mode = "none";
defparam \clk_in~I .input_register_mode = "none";
defparam \clk_in~I .output_register_mode = "none";
defparam \clk_in~I .oe_register_mode = "none";
defparam \clk_in~I .input_async_reset = "none";
defparam \clk_in~I .output_async_reset = "none";
defparam \clk_in~I .oe_async_reset = "none";
defparam \clk_in~I .input_sync_reset = "none";
defparam \clk_in~I .output_sync_reset = "none";
defparam \clk_in~I .oe_sync_reset = "none";
defparam \clk_in~I .input_power_up = "low";
defparam \clk_in~I .output_power_up = "low";
defparam \clk_in~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PLL_5
stratix_pll \pllx2_u1|altpll_component|pll (
	.fbin(vcc),
	.ena(vcc),
	.clkswitch(gnd),
	.areset(!\rst~combout ),
	.pfdena(vcc),
	.scanclk(),
	.scanaclr(gnd),
	.scandata(gnd),
	.comparator(gnd),
	.inclk({gnd,\clk_in~combout }),
	.clkena({vcc,vcc,vcc,vcc,vcc,vcc}),
	.extclkena({vcc,vcc,vcc,vcc}),
	.activeclock(),
	.clkloss(),
	.locked(\pllx2_u1|altpll_component|_locked ),
	.scandataout(),
	.enable0(),
	.enable1(),
	.clk(\ww_pllx2_u1|altpll_component|pll_clk ),
	.extclk(),
	.clkbad());
// synopsys translate_off
defparam \pllx2_u1|altpll_component|pll .operation_mode = "normal";
defparam \pllx2_u1|altpll_component|pll .pll_type = "enhanced";
defparam \pllx2_u1|altpll_component|pll .qualify_conf_done = "off";
defparam \pllx2_u1|altpll_component|pll .valid_lock_multiplier = 1;
defparam \pllx2_u1|altpll_component|pll .invalid_lock_multiplier = 5;
defparam \pllx2_u1|altpll_component|pll .compensate_clock = "clk0";
defparam \pllx2_u1|altpll_component|pll .inclk0_input_frequency = 20000;
defparam \pllx2_u1|altpll_component|pll .inclk1_input_frequency = 20000;
defparam \pllx2_u1|altpll_component|pll .pfd_min = 2380;
defparam \pllx2_u1|altpll_component|pll .pfd_max = 333333;
defparam \pllx2_u1|altpll_component|pll .vco_min = 1250;
defparam \pllx2_u1|altpll_component|pll .vco_max = 3334;
defparam \pllx2_u1|altpll_component|pll .vco_center = 1666;
defparam \pllx2_u1|altpll_component|pll .pll_compensation_delay = 4003;
defparam \pllx2_u1|altpll_component|pll .skip_vco = "off";
defparam \pllx2_u1|altpll_component|pll .primary_clock = "inclk0";
defparam \pllx2_u1|altpll_component|pll .switch_over_on_lossclk = "off";
defparam \pllx2_u1|altpll_component|pll .switch_over_on_gated_lock = "off";
defparam \pllx2_u1|altpll_component|pll .enable_switch_over_counter = "off";
defparam \pllx2_u1|altpll_component|pll .gate_lock_signal = "no";
defparam \pllx2_u1|altpll_component|pll .gate_lock_counter = 0;
defparam \pllx2_u1|altpll_component|pll .switch_over_counter = 1;
defparam \pllx2_u1|altpll_component|pll .m = 12;
defparam \pllx2_u1|altpll_component|pll .n = 1;
defparam \pllx2_u1|altpll_component|pll .m2 = 1;
defparam \pllx2_u1|altpll_component|pll .n2 = 1;
defparam \pllx2_u1|altpll_component|pll .charge_pump_current = 50;
defparam \pllx2_u1|altpll_component|pll .loop_filter_c = 10;
defparam \pllx2_u1|altpll_component|pll .loop_filter_r = "1.021000";
defparam \pllx2_u1|altpll_component|pll .clk0_counter = "g3";
defparam \pllx2_u1|altpll_component|pll .l0_mode = "even";
defparam \pllx2_u1|altpll_component|pll .l1_mode = "bypass";
defparam \pllx2_u1|altpll_component|pll .g0_mode = "bypass";
defparam \pllx2_u1|altpll_component|pll .g1_mode = "bypass";
defparam \pllx2_u1|altpll_component|pll .g2_mode = "bypass";
defparam \pllx2_u1|altpll_component|pll .g3_mode = "even";
defparam \pllx2_u1|altpll_component|pll .e0_mode = "bypass";
defparam \pllx2_u1|altpll_component|pll .e1_mode = "bypass";
defparam \pllx2_u1|altpll_component|pll .e2_mode = "bypass";
defparam \pllx2_u1|altpll_component|pll .e3_mode = "bypass";
defparam \pllx2_u1|altpll_component|pll .l0_high = 4;
defparam \pllx2_u1|altpll_component|pll .g3_high = 3;
defparam \pllx2_u1|altpll_component|pll .l0_low = 4;
defparam \pllx2_u1|altpll_component|pll .g3_low = 3;
defparam \pllx2_u1|altpll_component|pll .m_initial = 1;
defparam \pllx2_u1|altpll_component|pll .l0_initial = 1;
defparam \pllx2_u1|altpll_component|pll .g3_initial = 1;
defparam \pllx2_u1|altpll_component|pll .m_ph = 0;
defparam \pllx2_u1|altpll_component|pll .l0_ph = 0;
defparam \pllx2_u1|altpll_component|pll .l1_ph = 0;
defparam \pllx2_u1|altpll_component|pll .g0_ph = 0;
defparam \pllx2_u1|altpll_component|pll .g1_ph = 0;
defparam \pllx2_u1|altpll_component|pll .g2_ph = 0;
defparam \pllx2_u1|altpll_component|pll .g3_ph = 0;
defparam \pllx2_u1|altpll_component|pll .e0_ph = 0;
defparam \pllx2_u1|altpll_component|pll .e1_ph = 0;
defparam \pllx2_u1|altpll_component|pll .e2_ph = 0;
defparam \pllx2_u1|altpll_component|pll .e3_ph = 0;
defparam \pllx2_u1|altpll_component|pll .m_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .n_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .l0_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .l1_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .g0_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .g1_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .g2_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .g3_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .e0_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .e1_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .e2_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .e3_time_delay = 0;
defparam \pllx2_u1|altpll_component|pll .bandwidth_type = "auto";
defparam \pllx2_u1|altpll_component|pll .bandwidth = 910556;
defparam \pllx2_u1|altpll_component|pll .spread_frequency = 0;
defparam \pllx2_u1|altpll_component|pll .down_spread = "0 %";
defparam \pllx2_u1|altpll_component|pll .clk0_multiply_by = 2;
defparam \pllx2_u1|altpll_component|pll .clk1_multiply_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk2_multiply_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk3_multiply_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk4_multiply_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk5_multiply_by = 1;
defparam \pllx2_u1|altpll_component|pll .extclk0_multiply_by = 1;
defparam \pllx2_u1|altpll_component|pll .extclk1_multiply_by = 1;
defparam \pllx2_u1|altpll_component|pll .extclk2_multiply_by = 1;
defparam \pllx2_u1|altpll_component|pll .extclk3_multiply_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk0_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk1_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk2_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk3_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk4_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk5_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .extclk0_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .extclk1_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .extclk2_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .extclk3_divide_by = 1;
defparam \pllx2_u1|altpll_component|pll .clk0_phase_shift = "0";
defparam \pllx2_u1|altpll_component|pll .clk1_phase_shift = "0";
defparam \pllx2_u1|altpll_component|pll .clk2_phase_shift = "0";
defparam \pllx2_u1|altpll_component|pll .clk3_phase_shift = "0";
defparam \pllx2_u1|altpll_component|pll .clk4_phase_shift = "0";
defparam \pllx2_u1|altpll_component|pll .clk5_phase_shift = "0";
defparam \pllx2_u1|altpll_component|pll .extclk0_phase_shift = "0";