pll_ram_v.sdo

ModelSim对Altera设计进行功能仿真的简单操作步骤

    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE rd_addr\[4\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (976:976:976) (976:976:976))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_in\[1\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (976:976:976) (976:976:976))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_in\[2\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (976:976:976) (976:976:976))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_in\[3\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (976:976:976) (976:976:976))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_in\[4\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (976:976:976) (976:976:976))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_in\[5\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (976:976:976) (976:976:976))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_in\[6\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (976:976:976) (976:976:976))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_in\[7\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (976:976:976) (976:976:976))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_ram_register")
    (INSTANCE dpram8x32_u1\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portadatain_reg)
    (DELAY
      (ABSOLUTE
        (PORT data[0] (4421:4421:4421) (4421:4421:4421))
        (PORT data[1] (4431:4431:4431) (4431:4431:4431))
        (PORT data[2] (4785:4785:4785) (4785:4785:4785))
        (PORT data[3] (4429:4429:4429) (4429:4429:4429))
        (PORT data[4] (4427:4427:4427) (4427:4427:4427))
        (PORT data[5] (4746:4746:4746) (4746:4746:4746))
        (PORT data[6] (4654:4654:4654) (4654:4654:4654))
        (PORT data[7] (4415:4415:4415) (4415:4415:4415))
        (PORT clk (1871:1871:1871) (1871:1871:1871))
        (PORT aclr (2309:2309:2309) (2309:2309:2309))
        (IOPATH (posedge clk) dataout (467:467:467) (467:467:467))
        (IOPATH (posedge clk) done (467:467:467) (467:467:467))
        (IOPATH (posedge aclr) dataout (253:253:253) (253:253:253))
      )
    )
    (TIMINGCHECK
      (SETUP data (posedge clk) (149:149:149))
      (HOLD data (posedge clk) (38:38:38))
      (SETUP ena (posedge clk) (121:121:121))
      (HOLD ena (posedge clk) (13:13:13))
    )
  )
  (CELL
    (CELLTYPE "stratix_ram_register")
    (INSTANCE dpram8x32_u1\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portaaddr_reg)
    (DELAY
      (ABSOLUTE
        (PORT data[0] (1037:1037:1037) (1037:1037:1037))
        (PORT data[1] (1382:1382:1382) (1382:1382:1382))
        (PORT data[2] (1031:1031:1031) (1031:1031:1031))
        (PORT data[3] (1027:1027:1027) (1027:1027:1027))
        (PORT data[4] (1012:1012:1012) (1012:1012:1012))
        (PORT clk (1871:1871:1871) (1871:1871:1871))
        (PORT aclr (2325:2325:2325) (2325:2325:2325))
        (IOPATH (posedge clk) dataout (467:467:467) (467:467:467))
        (IOPATH (posedge clk) done (467:467:467) (467:467:467))
        (IOPATH (posedge aclr) dataout (253:253:253) (253:253:253))
      )
    )
    (TIMINGCHECK
      (SETUP data (posedge clk) (149:149:149))
      (HOLD data (posedge clk) (38:38:38))
      (SETUP ena (posedge clk) (121:121:121))
      (HOLD ena (posedge clk) (13:13:13))
    )
  )
  (CELL
    (CELLTYPE "stratix_ram_register")
    (INSTANCE dpram8x32_u1\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portawe_reg)
    (DELAY
      (ABSOLUTE
        (PORT data[0] (4846:4846:4846) (4846:4846:4846))
        (PORT clk (1871:1871:1871) (1871:1871:1871))
        (PORT aclr (2219:2219:2219) (2219:2219:2219))
        (IOPATH (posedge clk) dataout (467:467:467) (467:467:467))
        (IOPATH (posedge clk) done (467:467:467) (467:467:467))
        (IOPATH (posedge aclr) dataout (253:253:253) (253:253:253))
      )
    )
    (TIMINGCHECK
      (SETUP data (posedge clk) (149:149:149))
      (HOLD data (posedge clk) (38:38:38))
      (SETUP ena (posedge clk) (121:121:121))
      (HOLD ena (posedge clk) (13:13:13))
    )
  )
  (CELL
    (CELLTYPE "stratix_ram_register")
    (INSTANCE dpram8x32_u1\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portbaddr_reg)
    (DELAY
      (ABSOLUTE
        (PORT data[0] (4789:4789:4789) (4789:4789:4789))
        (PORT data[1] (4595:4595:4595) (4595:4595:4595))
        (PORT data[2] (4787:4787:4787) (4787:4787:4787))
        (PORT data[3] (4626:4626:4626) (4626:4626:4626))
        (PORT data[4] (4806:4806:4806) (4806:4806:4806))
        (PORT clk (1870:1870:1870) (1870:1870:1870))
        (PORT aclr (2300:2300:2300) (2300:2300:2300))
        (IOPATH (posedge clk) dataout (467:467:467) (467:467:467))
        (IOPATH (posedge clk) done (467:467:467) (467:467:467))
        (IOPATH (posedge aclr) dataout (253:253:253) (253:253:253))
      )
    )
    (TIMINGCHECK
      (SETUP data (posedge clk) (149:149:149))
      (HOLD data (posedge clk) (38:38:38))
      (SETUP ena (posedge clk) (121:121:121))
      (HOLD ena (posedge clk) (13:13:13))
    )
  )
  (CELL
    (CELLTYPE "stratix_ram_register")
    (INSTANCE dpram8x32_u1\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portbrewe_reg)
    (DELAY
      (ABSOLUTE
        (PORT data[0] (4754:4754:4754) (4754:4754:4754))
        (PORT clk (1846:1846:1846) (1846:1846:1846))
        (PORT aclr (2246:2246:2246) (2246:2246:2246))
        (IOPATH (posedge clk) dataout (467:467:467) (467:467:467))
        (IOPATH (posedge clk) done (467:467:467) (467:467:467))
        (IOPATH (posedge aclr) dataout (253:253:253) (253:253:253))
      )
    )
    (TIMINGCHECK
      (SETUP data (posedge clk) (149:149:149))
      (HOLD data (posedge clk) (38:38:38))
      (SETUP ena (posedge clk) (121:121:121))
      (HOLD ena (posedge clk) (13:13:13))
    )
  )
  (CELL
    (CELLTYPE "stratix_ram_internal")
    (INSTANCE dpram8x32_u1\|altsyncram_component\|auto_generated\|ram_block1a0.internal_ram)
    (DELAY
      (ABSOLUTE
        (IOPATH portawriteenable portadataout (3489:3489:3489) (3489:3489:3489))
        (IOPATH portadatain portadataout (3489:3489:3489) (3489:3489:3489))
        (IOPATH portaaddress portadataout (3489:3489:3489) (3489:3489:3489))
        (IOPATH portbwriteenable portbdataout (3284:3284:3284) (3284:3284:3284))
        (IOPATH portbreadenable portbdataout (3284:3284:3284) (3284:3284:3284))
        (IOPATH portbaddress portbdataout (3284:3284:3284) (3284:3284:3284))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_ram_register")
    (INSTANCE dpram8x32_u1\|altsyncram_component\|auto_generated\|ram_block1a0.ram_portbdataout_reg)
    (DELAY
      (ABSOLUTE
        (PORT clk (1858:1858:1858) (1858:1858:1858))
        (PORT aclr (2191:2191:2191) (2191:2191:2191))
        (IOPATH (posedge clk) dataout (546:546:546) (546:546:546))
        (IOPATH (posedge clk) done (546:546:546) (546:546:546))
        (IOPATH (posedge aclr) dataout (332:332:332) (332:332:332))
      )
    )
    (TIMINGCHECK
      (SETUP data (posedge clk) (149:149:149))
      (HOLD data (posedge clk) (38:38:38))
      (SETUP ena (posedge clk) (121:121:121))
      (HOLD ena (posedge clk) (13:13:13))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE clk_out\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (2075:2075:2075) (2075:2075:2075))
        (IOPATH datain padio (2500:2500:2500) (2500:2500:2500))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE lock\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1492:1492:1492) (1492:1492:1492))
        (IOPATH datain padio (3041:3041:3041) (3041:3041:3041))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE package_full\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1563:1563:1563) (1563:1563:1563))
        (IOPATH datain padio (2758:2758:2758) (2758:2758:2758))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_out\[7\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1537:1537:1537) (1537:1537:1537))
        (IOPATH datain padio (2758:2758:2758) (2758:2758:2758))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_out\[6\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1513:1513:1513) (1513:1513:1513))
        (IOPATH datain padio (2758:2758:2758) (2758:2758:2758))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_out\[5\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1524:1524:1524) (1524:1524:1524))
        (IOPATH datain padio (2758:2758:2758) (2758:2758:2758))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_out\[4\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1547:1547:1547) (1547:1547:1547))
        (IOPATH datain padio (2758:2758:2758) (2758:2758:2758))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_out\[3\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1549:1549:1549) (1549:1549:1549))
        (IOPATH datain padio (2758:2758:2758) (2758:2758:2758))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_out\[2\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1552:1552:1552) (1552:1552:1552))
        (IOPATH datain padio (2758:2758:2758) (2758:2758:2758))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_out\[1\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1524:1524:1524) (1524:1524:1524))
        (IOPATH datain padio (2758:2758:2758) (2758:2758:2758))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE data_out\[0\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1508:1508:1508) (1508:1508:1508))
        (IOPATH datain padio (2758:2758:2758) (2758:2758:2758))
      )
    )
  )
)