uart_regs.tan.qmsg

uart_regs core目录下为Altera的IP宏功能模块

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "wb_we_i pin wb_addr_i\[0\] register start_dlc 3.465 ns " "Info: Minimum slack time is 3.465 ns for clock wb_we_i between source pin wb_addr_i\[0\] and destination register start_dlc" { { "Info" "ITDB_FULL_TH_REQUIREMENT" "3.000 ns + register " "Info: + th requirement for source pin and destination register is 3.000 ns" {  } {  } 0} { "Info" "ITDB_SLACK_TH_RESULT" "-0.465 ns - " "Info: - th from clock to input pin is -0.465 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i destination 2.916 ns + Longest register " "Info: + Longest clock path from clock wb_we_i to destination register is 2.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns wb_we_i 1 CLK Pin_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_N3; Fanout = 43; CLK Node = 'wb_we_i'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { wb_we_i } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.560 ns) 2.916 ns start_dlc 2 REG LC_X25_Y26_N3 1 " "Info: 2: + IC(1.694 ns) + CELL(0.560 ns) = 2.916 ns; Loc. = LC_X25_Y26_N3; Fanout = 1; REG Node = 'start_dlc'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.254 ns" { wb_we_i start_dlc } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 41.91 % " "Info: Total cell delay = 1.222 ns ( 41.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns 58.09 % " "Info: Total interconnect delay = 1.694 ns ( 58.09 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.916 ns" { wb_we_i start_dlc } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.481 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns wb_addr_i\[0\] 1 PIN Pin_A20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_A20; Fanout = 24; PIN Node = 'wb_addr_i\[0\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { wb_addr_i[0] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.044 ns) + CELL(0.087 ns) 3.107 ns i77~22 2 COMB LC_X25_Y26_N2 6 " "Info: 2: + IC(2.044 ns) + CELL(0.087 ns) = 3.107 ns; Loc. = LC_X25_Y26_N2; Fanout = 6; COMB Node = 'i77~22'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.131 ns" { wb_addr_i[0] i77~22 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 160 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.235 ns) 3.481 ns start_dlc 3 REG LC_X25_Y26_N3 1 " "Info: 3: + IC(0.139 ns) + CELL(0.235 ns) = 3.481 ns; Loc. = LC_X25_Y26_N3; Fanout = 1; REG Node = 'start_dlc'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "0.374 ns" { i77~22 start_dlc } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.298 ns 37.29 % " "Info: Total cell delay = 1.298 ns ( 37.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.183 ns 62.71 % " "Info: Total interconnect delay = 2.183 ns ( 62.71 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.481 ns" { wb_addr_i[0] i77~22 start_dlc } "NODE_NAME" } } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.916 ns" { wb_we_i start_dlc } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.481 ns" { wb_addr_i[0] i77~22 start_dlc } "NODE_NAME" } } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.916 ns" { wb_we_i start_dlc } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.481 ns" { wb_addr_i[0] i77~22 start_dlc } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk int_o int_o~reg0 8.502 ns register " "Info: Minimum tco from clock clk to destination pin int_o through register int_o~reg0 is 8.502 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.241 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.905 ns) 0.905 ns clk 1 CLK Pin_A15 211 " "Info: 1: + IC(0.000 ns) + CELL(0.905 ns) = 0.905 ns; Loc. = Pin_A15; Fanout = 211; CLK Node = 'clk'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(0.560 ns) 3.241 ns int_o~reg0 2 REG LC_X23_Y26_N4 1 " "Info: 2: + IC(1.776 ns) + CELL(0.560 ns) = 3.241 ns; Loc. = LC_X23_Y26_N4; Fanout = 1; REG Node = 'int_o~reg0'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.336 ns" { clk int_o~reg0 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 484 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.465 ns 45.20 % " "Info: Total cell delay = 1.465 ns ( 45.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.776 ns 54.80 % " "Info: Total interconnect delay = 1.776 ns ( 54.80 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.241 ns" { clk int_o~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 484 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.085 ns + Shortest register pin " "Info: + Shortest register to pin delay is 5.085 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_o~reg0 1 REG LC_X23_Y26_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y26_N4; Fanout = 1; REG Node = 'int_o~reg0'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { int_o~reg0 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 484 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.327 ns) + CELL(2.758 ns) 5.085 ns int_o 2 PIN Pin_A5 0 " "Info: 2: + IC(2.327 ns) + CELL(2.758 ns) = 5.085 ns; Loc. = Pin_A5; Fanout = 0; PIN Node = 'int_o'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.085 ns" { int_o~reg0 int_o } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.758 ns 54.24 % " "Info: Total cell delay = 2.758 ns ( 54.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.327 ns 45.76 % " "Info: Total interconnect delay = 2.327 ns ( 45.76 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.085 ns" { int_o~reg0 int_o } "NODE_NAME" } } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.241 ns" { clk int_o~reg0 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.085 ns" { int_o~reg0 int_o } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "wb_addr_i\[0\] wb_dat_o\[5\] 10.597 ns Shortest " "Info: Shortest tpd from source pin wb_addr_i\[0\] to destination pin wb_dat_o\[5\] is 10.597 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns wb_addr_i\[0\] 1 PIN Pin_A20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_A20; Fanout = 24; PIN Node = 'wb_addr_i\[0\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { wb_addr_i[0] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.044 ns) + CELL(0.087 ns) 3.107 ns i77~22 2 COMB LC_X25_Y26_N2 6 " "Info: 2: + IC(2.044 ns) + CELL(0.087 ns) = 3.107 ns; Loc. = LC_X25_Y26_N2; Fanout = 6; COMB Node = 'i77~22'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.131 ns" { wb_addr_i[0] i77~22 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 160 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.808 ns) + CELL(0.332 ns) 5.247 ns i~1477 3 COMB LC_X25_Y25_N8 1 " "Info: 3: + IC(1.808 ns) + CELL(0.332 ns) = 5.247 ns; Loc. = LC_X25_Y25_N8; Fanout = 1; COMB Node = 'i~1477'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.140 ns" { i77~22 i~1477 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.592 ns) + CELL(2.758 ns) 10.597 ns wb_dat_o\[5\] 4 PIN Pin_AB21 0 " "Info: 4: + IC(2.592 ns) + CELL(2.758 ns) = 10.597 ns; Loc. = Pin_AB21; Fanout = 0; PIN Node = 'wb_dat_o\[5\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.350 ns" { i~1477 wb_dat_o[5] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_r