uart_regs.tan.qmsg

uart_regs core目录下为Altera的IP宏功能模块

{ "Info" "ITDB_FULL_SLACK_RESULT" "wb_we_i pin wb_addr_i\[2\] register scratch\[2\] 8.989 ns " "Info: Slack time is 8.989 ns for clock wb_we_i between source pin wb_addr_i\[2\] and destination register scratch\[2\]" { { "Info" "ITDB_FULL_TSU_REQUIREMENT" "12.000 ns + register " "Info: + tsu requirement for source pin and destination register is 12.000 ns" {  } {  } 0} { "Info" "ITDB_SLACK_TSU_RESULT" "3.011 ns - " "Info: - tsu from clock to input pin is 3.011 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.939 ns + Longest pin register " "Info: + Longest pin to register delay is 5.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns wb_addr_i\[2\] 1 PIN Pin_A24 23 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_A24; Fanout = 23; PIN Node = 'wb_addr_i\[2\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { wb_addr_i[2] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.363 ns) + CELL(0.459 ns) 3.798 ns i159~12 2 COMB LC_X25_Y27_N3 8 " "Info: 2: + IC(2.363 ns) + CELL(0.459 ns) = 3.798 ns; Loc. = LC_X25_Y27_N3; Fanout = 8; COMB Node = 'i159~12'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.822 ns" { wb_addr_i[2] i159~12 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 221 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.415 ns) + CELL(0.726 ns) 5.939 ns scratch\[2\] 3 REG LC_X24_Y24_N7 1 " "Info: 3: + IC(1.415 ns) + CELL(0.726 ns) = 5.939 ns; Loc. = LC_X24_Y24_N7; Fanout = 1; REG Node = 'scratch\[2\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.141 ns" { i159~12 scratch[2] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 218 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.161 ns 36.39 % " "Info: Total cell delay = 2.161 ns ( 36.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.778 ns 63.61 % " "Info: Total interconnect delay = 3.778 ns ( 63.61 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.939 ns" { wb_addr_i[2] i159~12 scratch[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 218 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i destination 2.938 ns - Shortest register " "Info: - Shortest clock path from clock wb_we_i to destination register is 2.938 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns wb_we_i 1 CLK Pin_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_N3; Fanout = 43; CLK Node = 'wb_we_i'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { wb_we_i } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.716 ns) + CELL(0.560 ns) 2.938 ns scratch\[2\] 2 REG LC_X24_Y24_N7 1 " "Info: 2: + IC(1.716 ns) + CELL(0.560 ns) = 2.938 ns; Loc. = LC_X24_Y24_N7; Fanout = 1; REG Node = 'scratch\[2\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.276 ns" { wb_we_i scratch[2] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 218 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 41.59 % " "Info: Total cell delay = 1.222 ns ( 41.59 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.716 ns 58.41 % " "Info: Total interconnect delay = 1.716 ns ( 58.41 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.938 ns" { wb_we_i scratch[2] } "NODE_NAME" } } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.939 ns" { wb_addr_i[2] i159~12 scratch[2] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.938 ns" { wb_we_i scratch[2] } "NODE_NAME" } } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.939 ns" { wb_addr_i[2] i159~12 scratch[2] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.938 ns" { wb_we_i scratch[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk wb_dat_o\[0\] uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a0~portb_address_reg0 18.054 ns memory " "Info: tco from clock clk to destination pin wb_dat_o\[0\] through memory uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a0~portb_address_reg0 is 18.054 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.072 ns + Longest memory " "Info: + Longest clock path from clock clk to source memory is 3.072 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.905 ns) 0.905 ns clk 1 CLK Pin_A15 211 " "Info: 1: + IC(0.000 ns) + CELL(0.905 ns) = 0.905 ns; Loc. = Pin_A15; Fanout = 211; CLK Node = 'clk'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.784 ns) + CELL(0.383 ns) 3.072 ns uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a0~portb_address_reg0 2 MEM M512_X26_Y27 10 " "Info: 2: + IC(1.784 ns) + CELL(0.383 ns) = 3.072 ns; Loc. = M512_X26_Y27; Fanout = 10; MEM Node = 'uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a0~portb_address_reg0'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.167 ns" { clk uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns 41.93 % " "Info: Total cell delay = 1.288 ns ( 41.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.784 ns 58.07 % " "Info: Total interconnect delay = 1.784 ns ( 58.07 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.072 ns" { clk uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.519 ns + " "Info: + Micro clock to output delay of source is 0.519 ns" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.463 ns + Longest memory pin " "Info: + Longest memory to pin delay is 14.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a0~portb_address_reg0 1 MEM M512_X26_Y27 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X26_Y27; Fanout = 10; MEM Node = 'uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a0~portb_address_reg0'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.066 ns) 3.066 ns uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|q_b\[2\] 2 MEM M512_X26_Y27 1 " "Info: 2: + IC(0.000 ns) + CELL(3.066 ns) = 3.066 ns; Loc. = M512_X26_Y27; Fanout = 1; MEM Node = 'uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|q_b\[2\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.066 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[2] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" 39 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.239 ns) + CELL(0.332 ns) 4.637 ns i23~7 3 COMB LC_X25_Y26_N5 1 " "Info: 3: + IC(1.239 ns) + CELL(0.332 ns) = 4.637 ns; Loc. = LC_X25_Y26_N5; Fanout = 1; COMB Node = 'i23~7'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "1.571 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[2] i23~7 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 123 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.087 ns) 5.815 ns i~138 4 COMB LC_X24_Y25_N9 1 " "Info: 4: + IC(1.091 ns) + CELL(0.087 ns) = 5.815 ns; Loc. = LC_X24_Y25_N9; Fanout = 1; COMB Node = 'i~138'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "1.178 ns" { i23~7 i~138 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.332 ns) 7.211 ns i~139 5 COMB LC_X24_Y27_N7 1 " "Info: 5: + IC(1.064 ns) + CELL(0.332 ns) = 7.211 ns; Loc. = LC_X24_Y27_N7; Fanout = 1; COMB Node = 'i~139'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "1.396 ns" { i~138 i~139 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.213 ns) 8.465 ns i~1486 6 COMB LC_X24_Y28_N7 1 " "Info: 6: + IC(1.041 ns) + CELL(0.213 ns) = 8.465 ns; Loc. = LC_X24_Y28_N7; Fanout = 1; COMB Node = 'i~1486'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "1.254 ns" { i~139 i~1486 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.240 ns) + CELL(2.758 ns) 14.463 ns wb_dat_o\[0\] 7 PIN Pin_AB16 0 " "Info: 7: + IC(3.240 ns) + CELL(2.758 ns) = 14.463 ns; Loc. = Pin_AB16; Fanout = 0; PIN Node = 'wb_dat_o\[0\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.998 ns" { i~1486 wb_dat_o[0] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.788 ns 46.93 % " "Info: Total cell delay = 6.788 ns ( 46.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.675 ns 53.07 % " "Info: Total interconnect delay = 7.675 ns ( 53.07 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "14.463 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[2] i23~7 i~138 i~139 i~1486 wb_dat_o[0] } "NODE_NAME" } } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.072 ns" { clk uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "14.463 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[2] i23~7 i~138 i~139 i~1486 wb_dat_o[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "wb_addr_i\[0\] wb_dat_o\[0\] 15.420 ns Longest " "Info: Longest tpd from source pin wb_addr_i\[0\] to destination pin wb_dat_o\[0\] is 15.420 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns wb_addr_i\[0\] 1 PIN Pin_A20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_A20; Fanout = 24; PIN Node = 'wb_addr_i\[0\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { wb_addr_i[0] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.337 ns) + CELL(0.459 ns) 6.772 ns i~138 2 COMB LC_X24_Y25_N9 1 " "Info: 2: + IC(5.337 ns) + CELL(0.459 ns) = 6.772 ns; Loc. = LC_X24_Y25_N9; Fanout = 1; COMB Node = 'i~138'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.796 ns" { wb_addr_i[0] i~138 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.332 ns) 8.168 ns i~139 3 COMB LC_X24_Y27_N7 1 " "Info: 3: + IC(1.064 ns) + CELL(0.332 ns) = 8.168 ns; Loc. = LC_X24_Y27_N7; Fanout = 1; COMB Node = 'i~139'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "1.396 ns" { i~138 i~139 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.213 ns) 9.422 ns i~1486 4 COMB LC_X24_Y28_N7 1 " "Info: 4: + IC(1.041 ns) + CELL(0.213 ns) = 9.422 ns; Loc. = LC_X24_Y28_N7; Fanout = 1; COMB Node = 'i~1486'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "1.254 ns" { i~139 i~1486 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.240 ns) + CELL(2.758 ns) 15.420 ns wb_dat_o\[0\] 5 PIN Pin_AB16 0 " "Info: 5: + IC(3.240 ns) + CELL(2.758 ns) = 15.420 ns; Loc. = Pin_AB16; Fanout = 0; PIN Node = 'wb_dat_o\[0\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "5.998 ns" { i~1486 wb_dat_o[0] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.738 ns 30.73 % " "Info: Total cell delay = 4.738 ns ( 30.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.682 ns 69.27 % " "Info: Total interconnect delay = 10.682 ns ( 69.27 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "15.420 ns" { wb_addr_i[0] i~138 i~139 i~1486 wb_dat_o[0] } "NODE_NAME" } } }  } 0}