uart_regs.tan.qmsg

uart_regs core目录下为Altera的IP宏功能模块

{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "wb_we_i " "Info: Assuming node wb_we_i is an undefined clock" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "wb_we_i" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk memory uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a0~portb_address_reg3 register uart_transmitter:transmitter\|parity_xor 2.602 ns " "Info: Slack time is 2.602 ns for clock clk between source memory uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a0~portb_address_reg3 and destination register uart_transmitter:transmitter\|parity_xor" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "196.46 MHz 5.09 ns " "Info: Fmax is 196.46 MHz (period= 5.09 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.340 ns + Largest memory register " "Info: + Largest memory to register requirement is 7.340 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "7.692 ns + " "Info: + Setup relationship between source and destination is 7.692 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.692 ns " "Info: + Latch edge is 7.692 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 7.692 ns 0.000 ns  50 " "Info: Clock period of Destination clock clk is 7.692 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 7.692 ns 0.000 ns  50 " "Info: Clock period of Source clock clk is 7.692 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.177 ns + Largest " "Info: + Largest clock skew is 0.177 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.237 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.905 ns) 0.905 ns clk 1 CLK Pin_A15 211 " "Info: 1: + IC(0.000 ns) + CELL(0.905 ns) = 0.905 ns; Loc. = Pin_A15; Fanout = 211; CLK Node = 'clk'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.772 ns) + CELL(0.560 ns) 3.237 ns uart_transmitter:transmitter\|parity_xor 2 REG LC_X5_Y24_N1 1 " "Info: 2: + IC(1.772 ns) + CELL(0.560 ns) = 3.237 ns; Loc. = LC_X5_Y24_N1; Fanout = 1; REG Node = 'uart_transmitter:transmitter\|parity_xor'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.332 ns" { clk uart_transmitter:transmitter|parity_xor } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_transmitter.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_transmitter.v" 66 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.465 ns 45.26 % " "Info: Total cell delay = 1.465 ns ( 45.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.772 ns 54.74 % " "Info: Total interconnect delay = 1.772 ns ( 54.74 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.237 ns" { clk uart_transmitter:transmitter|parity_xor } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.060 ns - Longest memory " "Info: - Longest clock path from clock clk to source memory is 3.060 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.905 ns) 0.905 ns clk 1 CLK Pin_A15 211 " "Info: 1: + IC(0.000 ns) + CELL(0.905 ns) = 0.905 ns; Loc. = Pin_A15; Fanout = 211; CLK Node = 'clk'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.772 ns) + CELL(0.383 ns) 3.060 ns uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a0~portb_address_reg3 2 MEM M512_X4_Y24 8 " "Info: 2: + IC(1.772 ns) + CELL(0.383 ns) = 3.060 ns; Loc. = M512_X4_Y24; Fanout = 8; MEM Node = 'uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a0~portb_address_reg3'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.155 ns" { clk uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns 42.09 % " "Info: Total cell delay = 1.288 ns ( 42.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.772 ns 57.91 % " "Info: Total interconnect delay = 1.772 ns ( 57.91 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.060 ns" { clk uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 } "NODE_NAME" } } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.237 ns" { clk uart_transmitter:transmitter|parity_xor } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.060 ns" { clk uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.519 ns - " "Info: - Micro clock to output delay of source is 0.519 ns" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_transmitter.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_transmitter.v" 66 -1 0 } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.237 ns" { clk uart_transmitter:transmitter|parity_xor } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.060 ns" { clk uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.738 ns - Longest memory register " "Info: - Longest memory to register delay is 4.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a0~portb_address_reg3 1 MEM M512_X4_Y24 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X4_Y24; Fanout = 8; MEM Node = 'uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a0~portb_address_reg3'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.066 ns) 3.066 ns uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|q_b\[7\] 2 MEM M512_X4_Y24 2 " "Info: 2: + IC(0.000 ns) + CELL(3.066 ns) = 3.066 ns; Loc. = M512_X4_Y24; Fanout = 2; MEM Node = 'uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|q_b\[7\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.066 ns" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[7] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" 39 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.459 ns) 4.013 ns uart_transmitter:transmitter\|i~1206 3 COMB LC_X5_Y24_N7 1 " "Info: 3: + IC(0.488 ns) + CELL(0.459 ns) = 4.013 ns; Loc. = LC_X5_Y24_N7; Fanout = 1; COMB Node = 'uart_transmitter:transmitter\|i~1206'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "0.947 ns" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[7] uart_transmitter:transmitter|i~1206 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.364 ns) 4.738 ns uart_transmitter:transmitter\|parity_xor 4 REG LC_X5_Y24_N1 1 " "Info: 4: + IC(0.361 ns) + CELL(0.364 ns) = 4.738 ns; Loc. = LC_X5_Y24_N1; Fanout = 1; REG Node = 'uart_transmitter:transmitter\|parity_xor'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "0.725 ns" { uart_transmitter:transmitter|i~1206 uart_transmitter:transmitter|parity_xor } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_transmitter.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_transmitter.v" 66 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.889 ns 82.08 % " "Info: Total cell delay = 3.889 ns ( 82.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.849 ns 17.92 % " "Info: Total interconnect delay = 0.849 ns ( 17.92 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "4.738 ns" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[7] uart_transmitter:transmitter|i~1206 uart_transmitter:transmitter|parity_xor } "NODE_NAME" } } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.237 ns" { clk uart_transmitter:transmitter|parity_xor } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "3.060 ns" { clk uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "4.738 ns" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[7] uart_transmitter:transmitter|i~1206 uart_transmitter:transmitter|parity_xor } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "wb_we_i register lcr\[7\] register dl\[7\] 326.16 MHz 3.066 ns Internal " "Info: Clock wb_we_i has Internal fmax of 326.16 MHz between source register lcr\[7\] and destination register dl\[7\] (period= 3.066 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.876 ns + Longest register register " "Info: + Longest register to register delay is 2.876 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcr\[7\] 1 REG LC_X24_Y27_N4 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y27_N4; Fanout = 25; REG Node = 'lcr\[7\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { lcr[7] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 177 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.337 ns) + CELL(0.459 ns) 1.796 ns dl\[7\]~155 2 COMB LC_X25_Y26_N3 8 " "Info: 2: + IC(1.337 ns) + CELL(0.459 ns) = 1.796 ns; Loc. = LC_X25_Y26_N3; Fanout = 8; COMB Node = 'dl\[7\]~155'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "1.796 ns" { lcr[7] dl[7]~155 } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 185 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.726 ns) 2.876 ns dl\[7\] 3 REG LC_X25_Y26_N0 4 " "Info: 3: + IC(0.354 ns) + CELL(0.726 ns) = 2.876 ns; Loc. = LC_X25_Y26_N0; Fanout = 4; REG Node = 'dl\[7\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "1.080 ns" { dl[7]~155 dl[7] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 185 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.185 ns 41.20 % " "Info: Total cell delay = 1.185 ns ( 41.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.691 ns 58.80 % " "Info: Total interconnect delay = 1.691 ns ( 58.80 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.876 ns" { lcr[7] dl[7]~155 dl[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i destination 2.916 ns + Shortest register " "Info: + Shortest clock path from clock wb_we_i to destination register is 2.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns wb_we_i 1 CLK Pin_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_N3; Fanout = 43; CLK Node = 'wb_we_i'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { wb_we_i } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.560 ns) 2.916 ns dl\[7\] 2 REG LC_X25_Y26_N0 4 " "Info: 2: + IC(1.694 ns) + CELL(0.560 ns) = 2.916 ns; Loc. = LC_X25_Y26_N0; Fanout = 4; REG Node = 'dl\[7\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.254 ns" { wb_we_i dl[7] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 185 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 41.91 % " "Info: Total cell delay = 1.222 ns ( 41.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns 58.09 % " "Info: Total interconnect delay = 1.694 ns ( 58.09 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.916 ns" { wb_we_i dl[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i source 2.920 ns - Longest register " "Info: - Longest clock path from clock wb_we_i to source register is 2.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns wb_we_i 1 CLK Pin_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_N3; Fanout = 43; CLK Node = 'wb_we_i'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "" { wb_we_i } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.698 ns) + CELL(0.560 ns) 2.920 ns lcr\[7\] 2 REG LC_X24_Y27_N4 25 " "Info: 2: + IC(1.698 ns) + CELL(0.560 ns) = 2.920 ns; Loc. = LC_X24_Y27_N4; Fanout = 25; REG Node = 'lcr\[7\]'" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.258 ns" { wb_we_i lcr[7] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 177 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 41.85 % " "Info: Total cell delay = 1.222 ns ( 41.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.698 ns 58.15 % " "Info: Total interconnect delay = 1.698 ns ( 58.15 % )" {  } {  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.920 ns" { wb_we_i lcr[7] } "NODE_NAME" } } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.916 ns" { wb_we_i dl[7] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.920 ns" { wb_we_i lcr[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 177 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 185 -1 0 } }  } 0}  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.876 ns" { lcr[7] dl[7]~155 dl[7] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.916 ns" { wb_we_i dl[7] } "NODE_NAME" } } } { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" "" "" { Report "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs_cmp.qrpt" Compiler "uart_regs" "UNKNOWN" "V1" "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/uart_regs.quartus_db" { Floorplan "" "" "2.920 ns" { wb_we_i lcr[7] } "NODE_NAME" } } }  } 0}