dds.map.qmsg

利用EDA硬件描述语言来实现DDS功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 14 11:55:55 2008 " "Info: Processing started: Mon Jan 14 11:55:55 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dds.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dds-art " "Info: Found design unit 1: dds-art" {  } { { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg1-art " "Info: Found design unit 1: reg1-art" {  } { { "reg1.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg1.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg1 " "Info: Found entity 1: reg1" {  } { { "reg1.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sum32.vhd 2 1 " "Warning: Using design file sum32.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sum32-art " "Info: Found design unit 1: sum32-art" {  } { { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sum32 " "Info: Found entity 1: sum32" {  } { { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sum32 sum32:u0 " "Info: Elaborating entity \"sum32\" for hierarchy \"sum32:u0\"" {  } { { "dds.vhd" "u0" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 41 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp sum32.vhd(25) " "Warning (10492): VHDL Process Statement warning at sum32.vhd(25): signal \"temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg1 reg1:u1 " "Info: Elaborating entity \"reg1\" for hierarchy \"reg1:u1\"" {  } { { "dds.vhd" "u1" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 42 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "adder32.vhd 2 1 " "Warning: Using design file adder32.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder32-art " "Info: Found design unit 1: adder32-art" {  } { { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adder32 " "Info: Found entity 1: adder32" {  } { { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder32 adder32:u2 " "Info: Elaborating entity \"adder32\" for hierarchy \"adder32:u2\"" {  } { { "dds.vhd" "u2" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 43 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "b adder32.vhd(21) " "Warning (10492): VHDL Process Statement warning at adder32.vhd(21): signal \"b\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "reg2.vhd 2 1 " "Warning: Using design file reg2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg2-art " "Info: Found design unit 1: reg2-art" {  } { { "reg2.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg2.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg2 " "Info: Found entity 1: reg2" {  } { { "reg2.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg2.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg2 reg2:u3 " "Info: Elaborating entity \"reg2\" for hierarchy \"reg2:u3\"" {  } { { "dds.vhd" "u3" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 44 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "227 " "Info: Implemented 227 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "67 " "Info: Implemented 67 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "128 " "Info: Implemented 128 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 14 11:55:58 2008 " "Info: Processing ended: Mon Jan 14 11:55:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}