adder32.tan.qmsg

利用EDA硬件描述语言来实现DDS功能

{ "Info" "ITDB_TSU_RESULT" "b\[31\] a\[0\] clk 4.726 ns register " "Info: tsu for register \"b\[31\]\" (data pin = \"a\[0\]\", clock pin = \"clk\") is 4.726 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.725 ns + Longest pin register " "Info: + Longest pin to register delay is 7.725 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns a\[0\] 1 PIN PIN_J21 2 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_J21; Fanout = 2; PIN Node = 'a\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.669 ns) + CELL(0.524 ns) 6.427 ns b\[0\]~1064 2 COMB LC_X7_Y4_N4 6 " "Info: 2: + IC(4.669 ns) + CELL(0.524 ns) = 6.427 ns; Loc. = LC_X7_Y4_N4; Fanout = 6; COMB Node = 'b\[0\]~1064'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.193 ns" { a[0] b[0]~1064 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.142 ns) 6.569 ns b\[5\]~1069 3 COMB LC_X7_Y4_N9 6 " "Info: 3: + IC(0.000 ns) + CELL(0.142 ns) = 6.569 ns; Loc. = LC_X7_Y4_N9; Fanout = 6; COMB Node = 'b\[5\]~1069'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.142 ns" { b[0]~1064 b[5]~1069 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.098 ns) 6.667 ns b\[10\]~1074 4 COMB LC_X7_Y3_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.098 ns) = 6.667 ns; Loc. = LC_X7_Y3_N4; Fanout = 6; COMB Node = 'b\[10\]~1074'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.098 ns" { b[5]~1069 b[10]~1074 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.142 ns) 6.809 ns b\[15\]~1079 5 COMB LC_X7_Y3_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.142 ns) = 6.809 ns; Loc. = LC_X7_Y3_N9; Fanout = 6; COMB Node = 'b\[15\]~1079'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.142 ns" { b[10]~1074 b[15]~1079 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.098 ns) 6.907 ns b\[20\]~1084 6 COMB LC_X7_Y2_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.098 ns) = 6.907 ns; Loc. = LC_X7_Y2_N4; Fanout = 6; COMB Node = 'b\[20\]~1084'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.098 ns" { b[15]~1079 b[20]~1084 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.142 ns) 7.049 ns b\[25\]~1089 7 COMB LC_X7_Y2_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.142 ns) = 7.049 ns; Loc. = LC_X7_Y2_N9; Fanout = 6; COMB Node = 'b\[25\]~1089'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.142 ns" { b[20]~1084 b[25]~1089 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.098 ns) 7.147 ns b\[30\]~1094 8 COMB LC_X7_Y1_N4 1 " "Info: 8: + IC(0.000 ns) + CELL(0.098 ns) = 7.147 ns; Loc. = LC_X7_Y1_N4; Fanout = 1; COMB Node = 'b\[30\]~1094'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.098 ns" { b[25]~1089 b[30]~1094 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.578 ns) 7.725 ns b\[31\] 9 REG LC_X7_Y1_N5 1 " "Info: 9: + IC(0.000 ns) + CELL(0.578 ns) = 7.725 ns; Loc. = LC_X7_Y1_N5; Fanout = 1; REG Node = 'b\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.578 ns" { b[30]~1094 b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 39.56 % ) " "Info: Total cell delay = 3.056 ns ( 39.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.669 ns ( 60.44 % ) " "Info: Total interconnect delay = 4.669 ns ( 60.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.725 ns" { a[0] b[0]~1064 b[5]~1069 b[10]~1074 b[15]~1079 b[20]~1084 b[25]~1089 b[30]~1094 b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.725 ns" { a[0] a[0]~out0 b[0]~1064 b[5]~1069 b[10]~1074 b[15]~1079 b[20]~1084 b[25]~1089 b[30]~1094 b[31] } { 0.000ns 0.000ns 4.669ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.234ns 0.524ns 0.142ns 0.098ns 0.142ns 0.098ns 0.142ns 0.098ns 0.578ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.009 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 32 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns b\[31\] 2 REG LC_X7_Y1_N5 1 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X7_Y1_N5; Fanout = 1; REG Node = 'b\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.181 ns" { clk b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 b[31] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.725 ns" { a[0] b[0]~1064 b[5]~1069 b[10]~1074 b[15]~1079 b[20]~1084 b[25]~1089 b[30]~1094 b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.725 ns" { a[0] a[0]~out0 b[0]~1064 b[5]~1069 b[10]~1074 b[15]~1079 b[20]~1084 b[25]~1089 b[30]~1094 b[31] } { 0.000ns 0.000ns 4.669ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.234ns 0.524ns 0.142ns 0.098ns 0.142ns 0.098ns 0.142ns 0.098ns 0.578ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 b[31] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out2\[0\] b\[0\] 8.246 ns register " "Info: tco from clock \"clk\" to destination pin \"out2\[0\]\" through register \"b\[0\]\" is 8.246 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.997 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 32 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.627 ns) + CELL(0.542 ns) 2.997 ns b\[0\] 2 REG LC_X7_Y4_N4 1 " "Info: 2: + IC(1.627 ns) + CELL(0.542 ns) = 2.997 ns; Loc. = LC_X7_Y4_N4; Fanout = 1; REG Node = 'b\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.169 ns" { clk b[0] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.71 % ) " "Info: Total cell delay = 1.370 ns ( 45.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.627 ns ( 54.29 % ) " "Info: Total interconnect delay = 1.627 ns ( 54.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.997 ns" { clk b[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.997 ns" { clk clk~out0 b[0] } { 0.000ns 0.000ns 1.627ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.093 ns + Longest register pin " "Info: + Longest register to pin delay is 5.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b\[0\] 1 REG LC_X7_Y4_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N4; Fanout = 1; REG Node = 'b\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { b[0] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.689 ns) + CELL(2.404 ns) 5.093 ns out2\[0\] 2 PIN PIN_A17 0 " "Info: 2: + IC(2.689 ns) + CELL(2.404 ns) = 5.093 ns; Loc. = PIN_A17; Fanout = 0; PIN Node = 'out2\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.093 ns" { b[0] out2[0] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 47.20 % ) " "Info: Total cell delay = 2.404 ns ( 47.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.689 ns ( 52.80 % ) " "Info: Total interconnect delay = 2.689 ns ( 52.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.093 ns" { b[0] out2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.093 ns" { b[0] out2[0] } { 0.000ns 2.689ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.997 ns" { clk b[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.997 ns" { clk clk~out0 b[0] } { 0.000ns 0.000ns 1.627ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.093 ns" { b[0] out2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.093 ns" { b[0] out2[0] } { 0.000ns 2.689ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "b\[31\] n\[31\] clk -2.049 ns register " "Info: th for register \"b\[31\]\" (data pin = \"n\[31\]\", clock pin = \"clk\") is -2.049 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.009 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 32 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns b\[31\] 2 REG LC_X7_Y1_N5 1 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X7_Y1_N5; Fanout = 1; REG Node = 'b\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.181 ns" { clk b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 b[31] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.158 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.158 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns n\[31\] 1 PIN PIN_Y17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y17; Fanout = 1; PIN Node = 'n\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { n[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.848 ns) + CELL(0.223 ns) 5.158 ns b\[31\] 2 REG LC_X7_Y1_N5 1 " "Info: 2: + IC(3.848 ns) + CELL(0.223 ns) = 5.158 ns; Loc. = LC_X7_Y1_N5; Fanout = 1; REG Node = 'b\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.071 ns" { n[31] b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns ( 25.40 % ) " "Info: Total cell delay = 1.310 ns ( 25.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.848 ns ( 74.60 % ) " "Info: Total interconnect delay = 3.848 ns ( 74.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.158 ns" { n[31] b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.158 ns" { n[31] n[31]~out0 b[31] } { 0.000ns 0.000ns 3.848ns } { 0.000ns 1.087ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 b[31] } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.158 ns" { n[31] b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.158 ns" { n[31] n[31]~out0 b[31] } { 0.000ns 0.000ns 3.848ns } { 0.000ns 1.087ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 14 13:02:15 2008 " "Info: Processing ended: Mon Jan 14 13:02:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}