sum32.vhd

来自「利用EDA硬件描述语言来实现DDS功能」· VHDL 代码 · 共 28 行

library ieee;---------32位累加器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sum32 is
   port(k: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        en:in std_logic;
        reset:in std_logic;
         out1:out std_logic_vector(31 downto 0));
end entity sum32;
architecture art  of sum32 is
  signal temp:std_logic_vector(31 downto 0);
begin
process(clk,en,reset) is
  begin 
  if reset='1'then
    temp<="00000000000000000000000000000000";
else
if clk'event and clk='1'then
   if en='1'then
      temp<=temp+k;
    end if;
   end if;
  end if;
  out1<=temp;
end process;
end architecture art;