filtro_fir_mac.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity filtro_fir_mac is
	Generic ( 	data : integer := 8;
				num1 : integer := 3;
				num2 : integer := 8;
				tam_entrada : integer := 8;
				tam_salida  : integer :=23);
    Port ( 	entrada : in std_logic_vector(7 downto 0);
			salida 	: out std_logic_vector(22 downto 0);
			sel		: in std_logic_vector(1 downto 0);
			reset 	: in std_logic;
			enable	: in std_logic;
			clk 		: in std_logic);
end filtro_fir_mac;

architecture Behavioral of filtro_fir_mac is

	signal cnt : std_logic_vector(2 downto 0);
	
	signal r0 : std_logic_vector(7 downto 0):=(others=>'0');
	signal r1 : std_logic_vector(7 downto 0):=(others=>'0');
	signal r2 : std_logic_vector(7 downto 0):=(others=>'0');
	signal r3 : std_logic_vector(7 downto 0):=(others=>'0');
	signal r4 : std_logic_vector(7 downto 0):=(others=>'0');
	signal r5 : std_logic_vector(7 downto 0):=(others=>'0');
	signal r6 : std_logic_vector(7 downto 0):=(others=>'0');
	signal r7 : std_logic_vector(7 downto 0):=(others=>'0');
	signal load : std_logic:='0';
	
	signal sal_rom1 : std_logic_vector(7 downto 0);
	signal sal_rom2 : std_logic_vector(7 downto 0);
	signal sal_rom3 : std_logic_vector(7 downto 0);
	signal sal_rom4 : std_logic_vector(7 downto 0);

	signal sal_mux : std_logic_vector(7 downto 0):=(others=>'0');
	signal sal_mux_coef : std_logic_vector(7 downto 0):=(others=>'0');
	signal sal_mult : std_logic_vector(15 downto 0):=(others=>'0');
	signal sal_sum : std_logic_vector(22 downto 0):=(others=>'0');

	signal ent_acu : std_logic_vector(22 downto 0):=(others=>'0');	
	signal reg_acu : std_logic_vector(22 downto 0):=(others=>'0');


	signal count_aux : unsigned (2 downto 0);

	--Declaracion de Rom Asincrona
	component c_rom_1 is
	 	Generic (data_width : integer:= 8;
				   address_width : integer:= 3;
				   mem_depth : integer:= 8);
    	Port (   address : in std_logic_vector(address_width-1 downto 0);
      	      data_out : out std_logic_vector(data_width-1 downto 0));
	end component;

	component c_rom_2 is
	 	Generic (data_width : integer:= 8;
				   address_width : integer:= 3;
				   mem_depth : integer:= 8);
    	Port (   address : in std_logic_vector(address_width-1 downto 0);
      	      data_out : out std_logic_vector(data_width-1 downto 0));
	end component;

	component c_rom_3 is
	 	Generic (data_width : integer:= 8;
				   address_width : integer:= 3;
				   mem_depth : integer:= 8);
    	Port (   address : in std_logic_vector(address_width-1 downto 0);
      	      data_out : out std_logic_vector(data_width-1 downto 0));
	end component;

	component c_rom_4 is
	 	Generic (data_width : integer:= 8;
				   address_width : integer:= 3;
				   mem_depth : integer:= 8);
    	Port (   address : in std_logic_vector(address_width-1 downto 0);
      	      data_out : out std_logic_vector(data_width-1 downto 0));
	end component;

	--Declaracion de Registro
	component registro is
			Generic ( tam : integer :=8);
		    Port ( inbus : in std_logic_vector(tam-1 downto 0);
	           	   outbus : out std_logic_vector(tam-1 downto 0);
   	               reset : in std_logic;
      	           load : in std_logic;
				   clk : in std_logic);
	end component;


begin
	--c_rom : Instanciacion de rom_asincrona
	c_1 : c_rom_1 
		Generic map ( data_width => data,
					  address_width => num1,
					  mem_depth => num2)
		Port map ( address=>cnt,data_out=>sal_rom1);
	
	c_2 : c_rom_2 
		Generic map ( data_width => data,
					  address_width => num1,
					  mem_depth => num2)
		Port map ( address=>cnt,data_out=>sal_rom2);
		
	c_3 : c_rom_3 
		Generic map ( data_width => data,
					  address_width => num1,
					  mem_depth => num2)
		Port map ( address=>cnt,data_out=>sal_rom3);
		
	c_4 : c_rom_4 
		Generic map ( data_width => data,
					  address_width => num1,
					  mem_depth => num2)
		Port map ( address=>cnt,data_out=>sal_rom4);

	--registros que almacenan valores entrada
	registro0 : registro 
		Generic map (tam=>tam_entrada)
		port map (inbus=>entrada,outbus=>r0,reset=>reset,load=>load,clk=>clk);
	registro1 : registro
		Generic map (tam=>tam_entrada)
		port map (inbus=>r0,outbus=>r1,reset=>reset,load=>load,clk=>clk);
	registro2 : registro
		Generic map (tam=>tam_entrada)
		port map (inbus=>r1,outbus=>r2,reset=>reset,load=>load,clk=>clk);
	registro3 : registro
		Generic map (tam=>tam_entrada)
		port map (inbus=>r2,outbus=>r3,reset=>reset,load=>load,clk=>clk);
	registro4 : registro
		Generic map (tam=>tam_entrada)
		port map (inbus=>r3,outbus=>r4,reset=>reset,load=>load,clk=>clk);
	registro5 : registro
		Generic map (tam=>tam_entrada)
		port map (inbus=>r4,outbus=>r5,reset=>reset,load=>load,clk=>clk);
	registro6 : registro
		Generic map (tam=>tam_entrada)
		port map (inbus=>r5,outbus=>r6,reset=>reset,load=>load,clk=>clk);
	registro7 : registro
		Generic map (tam=>tam_entrada)
		port map (inbus=>r6,outbus=>r7,reset=>reset,load=>load,clk=>clk);

	--registro salida
	registro_salida : registro
		Generic map (tam=>tam_salida)
		port map (inbus=>sal_sum,outbus=>salida,reset=>reset,load=>load,clk=>clk);

	--contador
	process(clk,reset,enable)
	begin
		if reset='1' then
			count_aux<=(others =>'0');
		elsif rising_edge(clk) then
			if enable = '1' then
				count_aux<=count_aux+1;
			end if;
		end if;
	end process;
	cnt<=std_logic_vector(count_aux);

	--Multiplexor del buffer
	process (cnt,r0,r1,r2,r3,r4,r5,r6,r7)
	begin
		case cnt is
			when "000" =>
				sal_mux<=r0;
			when "001" =>
				sal_mux<=r1;
			when "010" =>
				sal_mux<=r2;
			when "011" =>
				sal_mux<=r3;
			when "100" =>
				sal_mux<=r4;
			when "101" =>
				sal_mux<=r5;
			when "110" =>
				sal_mux<=r6;
			when "111" =>
				sal_mux<=r7;
			when others =>
				sal_mux<=sal_mux;
		end case;
	end process;
	
	--Multiplexor para las memorias de coeficientes.
	process (sal_rom1,sal_rom2,sal_rom3,sal_rom4,sel)
	begin
		case sel is
			when "00" =>
				sal_mux_coef<=sal_rom1;
			when "01" =>
				sal_mux_coef<=sal_rom2;
			when "10" =>
				sal_mux_coef<=sal_rom3;
			when "11" =>
				sal_mux_coef<=sal_rom4;
			when others =>
				sal_mux_coef<=sal_mux_coef;
		end case;
	end process;

	--multiplicador  (la salida sera de 16 bits = 2*8bits)
	sal_mult<=std_logic_vector(signed(sal_mux)*signed(sal_mux_coef));

	sal_sum<=std_logic_vector(signed(reg_acu)+signed(sal_mult));
	ent_acu<=sal_sum;

	--registro acumulador
	process(reset,clk)
	begin
		if (reset='1') then
			reg_acu<=(others=>'0');
		elsif (rising_edge(clk)) then
			if enable = '1' then
				if (cnt="111")	then
					reg_acu<=ent_acu;
				end if;
			end if;
		end if;
	end process;

	--se馻l de carga 
	process(cnt)
	begin
		if (cnt="111") then
			load<='1';
		else
			load<='0';
		end if;
	end process;

end Behavioral;