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Number of 4 input LUTs: 75 out of 4704 1% Number of bonded IOBs: 29 out of 146 19% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 109 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 17.375ns (Maximum Frequency: 57.554MHz) Minimum input arrival time before clock: 2.441ns Maximum output required time after clock: 6.514ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/Practicas/filtro_fir/rom_asincrona.vhd" in Library work.Architecture behavioral of Entity rom_asincrona is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <rom_asincrona> (Architecture <behavioral>).Entity <rom_asincrona> analyzed. Unit <rom_asincrona> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <rom_asincrona>. Related source file is "C:/Practicas/filtro_fir/rom_asincrona.vhd".WARNING:Xst:647 - Input <address> is never used.Unit <rom_asincrona> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <rom_asincrona> ...Loading device for application Rf_Device from file '2s200e.nph' in environment C:/XilinxISE71.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block rom_asincrona, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200epq208-6 Number of bonded IOBs: 11 out of 146 7% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/Practicas/filtro_fir/rom_asincrona.vhd" in Library work.Architecture behavioral of Entity rom_asincrona is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <rom_asincrona> (Architecture <behavioral>).Entity <rom_asincrona> analyzed. Unit <rom_asincrona> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <rom_asincrona>. Related source file is "C:/Practicas/filtro_fir/rom_asincrona.vhd".WARNING:Xst:647 - Input <address> is never used.Unit <rom_asincrona> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <rom_asincrona> ...Loading device for application Rf_Device from file '2s200e.nph' in environment C:/XilinxISE71.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block rom_asincrona, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200epq208-6 Number of bonded IOBs: 11 out of 146 7% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/Practicas/filtro_fir/rom_asincrona.vhd" in Library work.Architecture behavioral of Entity rom_asincrona is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <rom_asincrona> (Architecture <behavioral>).Entity <rom_asincrona> analyzed. Unit <rom_asincrona> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <rom_asincrona>. Related source file is "C:/Practicas/filtro_fir/rom_asincrona.vhd".WARNING:Xst:647 - Input <address> is never used.Unit <rom_asincrona> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <rom_asincrona> ...Loading device for application Rf_Device from file '2s200e.nph' in environment C:/XilinxISE71.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block rom_asincrona, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200epq208-6 Number of bonded IOBs: 11 out of 146 7% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/Practicas/filtro_fir/rom_asincrona.vhd" in Library work.Architecture behavioral of Entity rom_asincrona is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <rom_asincrona> (Architecture <behavioral>).Entity <rom_asincrona> analyzed. Unit <rom_asincrona> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <rom_asincrona>. Related source file is "C:/Practicas/filtro_fir/rom_asincrona.vhd".WARNING:Xst:647 - Input <address> is never used.Unit <rom_asincrona> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================⌨️ 快捷键说明
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