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This sources implement a 8-bit FIR Filter with selectable coefficent rom.

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Practicas/filtro_fir/rom_asincrona.vhd" in Library work.
Entity <rom_asincrona> compiled.
Entity <rom_asincrona> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rom_asincrona> (Architecture <Behavioral>).
ERROR:Xst:1740 - "C:/Practicas/filtro_fir/rom_asincrona.vhd" line 38: Size of expression does not match size of type.
--> 

Total memory usage is 75620 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Practicas/filtro_fir/rom_asincrona.vhd" in Library work.
Entity <rom_asincrona> compiled.
Entity <rom_asincrona> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rom_asincrona> (Architecture <behavioral>).
Entity <rom_asincrona> analyzed. Unit <rom_asincrona> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <rom_asincrona>.
    Related source file is "C:/Practicas/filtro_fir/rom_asincrona.vhd".
Unit <rom_asincrona> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <rom_asincrona> ...
Loading device for application Rf_Device from file '2s200e.nph' in environment C:/XilinxISE71.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block rom_asincrona, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of bonded IOBs:                 13  out of    146     8%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Practicas/filtro_fir/rom_asincrona.vhd" in Library work.
Architecture behavioral of Entity rom_asincrona is up to date.
Compiling vhdl file "C:/Practicas/filtro_fir/registro.vhd" in Library work.
Entity <registro> compiled.
Entity <registro> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/Practicas/filtro_fir/filtro_fir_mac.vhd" in Library work.
Entity <filtro_fir_mac> compiled.
Entity <filtro_fir_mac> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <filtro_fir_mac> (Architecture <Behavioral>).
INFO:Xst:1561 - "C:/Practicas/filtro_fir/filtro_fir_mac.vhd" line 149: Mux is complete : default of case is discarded
Entity <filtro_fir_mac> analyzed. Unit <filtro_fir_mac> generated.

Analyzing generic Entity <rom_asincrona> (Architecture <behavioral>).
	data_width = 8
	address_width = 3
	mem_depth = 8
ERROR:Xst:778 - "C:/Practicas/filtro_fir/rom_asincrona.vhd" line 38: Bad aggregate specification.
--> 

Total memory usage is 75620 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Practicas/filtro_fir/rom_asincrona.vhd" in Library work.
Entity <rom_asincrona> compiled.
Entity <rom_asincrona> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/Practicas/filtro_fir/registro.vhd" in Library work.
Architecture behavioral of Entity registro is up to date.
Compiling vhdl file "C:/Practicas/filtro_fir/filtro_fir_mac.vhd" in Library work.
Architecture behavioral of Entity filtro_fir_mac is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <filtro_fir_mac> (Architecture <behavioral>).
INFO:Xst:1561 - "C:/Practicas/filtro_fir/filtro_fir_mac.vhd" line 149: Mux is complete : default of case is discarded
Entity <filtro_fir_mac> analyzed. Unit <filtro_fir_mac> generated.

Analyzing generic Entity <rom_asincrona> (Architecture <behavioral>).
	data_width = 8
	address_width = 3
	mem_depth = 8
Entity <rom_asincrona> analyzed. Unit <rom_asincrona> generated.

Analyzing generic Entity <registro> (Architecture <behavioral>).
	tam = 8
Entity <registro> analyzed. Unit <registro> generated.

Analyzing generic Entity <registro.0> (Architecture <behavioral>).
	tam = 20
Entity <registro.0> analyzed. Unit <registro.0> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <registro_0>.
    Related source file is "C:/Practicas/filtro_fir/registro.vhd".
WARNING:Xst:1305 - Output <outbus> is never assigned. Tied to value 00000000000000000000.
WARNING:Xst:646 - Signal <M> is assigned but never used.
Unit <registro_0> synthesized.


Synthesizing Unit <registro>.
    Related source file is "C:/Practicas/filtro_fir/registro.vhd".
WARNING:Xst:1305 - Output <outbus> is never assigned. Tied to value 00000000.
WARNING:Xst:646 - Signal <M> is assigned but never used.
Unit <registro> synthesized.


Synthesizing Unit <rom_asincrona>.
    Related source file is "C:/Practicas/filtro_fir/rom_asincrona.vhd".
WARNING:Xst:647 - Input <address> is never used.
Unit <rom_asincrona> synthesized.


Synthesizing Unit <filtro_fir_mac>.
    Related source file is "C:/Practicas/filtro_fir/filtro_fir_mac.vhd".
WARNING:Xst:653 - Signal <reset> is used but never assigned. Tied to value 1.
    Found 3-bit up counter for signal <count_aux>.
    Found 20-bit register for signal <reg_acu>.
    Found 8x8-bit multiplier for signal <sal_mult>.
    Found 8-bit 8-to-1 multiplexer for signal <sal_mux>.
    Found 20-bit adder for signal <sal_sum>.
    Summary:
	inferred   1 Counter(s).
	inferred  20 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
	inferred   8 Multiplexer(s).
Unit <filtro_fir_mac> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Multipliers                      : 1
 8x8-bit multiplier                : 1
# Adders/Subtractors               : 1
 20-bit adder                      : 1
# Counters                         : 1
 3-bit up counter                  : 1
# Registers                        : 1
 20-bit register                   : 1
# Multiplexers                     : 1
 8-bit 8-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <count_aux_1> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_19> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_15> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_16> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_17> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_18> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <count_aux_2> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <count_aux_0> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_0> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_1> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_2> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_3> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_4> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_5> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_6> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_7> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_8> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_9> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_10> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_11> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_12> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_13> is unconnected in block <filtro_fir_mac>.
WARNING:Xst:1291 - FF/Latch <reg_acu_14> is unconnected in block <filtro_fir_mac>.

Optimizing unit <filtro_fir_mac> ...
Loading device for application Rf_Device from file '2s200e.nph' in environment C:/XilinxISE71.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block filtro_fir_mac, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of bonded IOBs:                 29  out of    146    19%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6