registro.vhd

来自「This sources implement a 8-bit FIR Filte」· VHDL 代码 · 共 33 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity registro is
	 Generic ( tam : integer :=8);
    Port ( inbus : in std_logic_vector(tam-1 downto 0);
           outbus : out std_logic_vector(tam-1 downto 0);
           reset : in std_logic;
           load : in std_logic;
			  clk : in std_logic);
end registro;

architecture Behavioral of registro is

	signal M : std_logic_vector(tam-1 downto 0);

begin
	process(reset,clk)
	begin
		if (reset='1') then
			M<=(others=>'0');
		elsif (rising_edge(clk)) then
			if load='1' then
				M<=inbus;
			end if;
		end if;
	end process;
	outbus<=M;

end Behavioral;