filtro_fir_mac_synthesis.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

      LO => N6
    );
  filtro_fir_mac_sal_sum_3_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_2_cyo,
      DI => reg_acu(3),
      S => N6,
      O => filtro_fir_mac_sal_sum_3_cyo
    );
  filtro_fir_mac_sal_sum_3_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_2_cyo,
      LI => N6,
      O => sal_sum(3)
    );
  Mmult_sal_mult_inst_lut2_301 : LUT4_L
    generic map(
      INIT => X"965A"
    )
    port map (
      I0 => Mmult_sal_mult_N43,
      I1 => salida_rom_5_Q,
      I2 => Mmult_sal_mult_N21,
      I3 => sal_mux(0),
      LO => Mmult_sal_mult_inst_lut2_30
    );
  filtro_fir_mac_sal_sum_4_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_3_cyo,
      DI => reg_acu(4),
      S => N7,
      O => filtro_fir_mac_sal_sum_4_cyo
    );
  filtro_fir_mac_sal_sum_4_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_3_cyo,
      LI => N7,
      O => sal_sum(4)
    );
  filtro_fir_mac_sal_sum_5_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(5),
      I1 => sal_mult_5_Q,
      LO => N8
    );
  filtro_fir_mac_sal_sum_5_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_4_cyo,
      DI => reg_acu(5),
      S => N8,
      O => filtro_fir_mac_sal_sum_5_cyo
    );
  filtro_fir_mac_sal_sum_5_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_4_cyo,
      LI => N8,
      O => sal_sum(5)
    );
  filtro_fir_mac_sal_sum_6_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(6),
      I1 => sal_mult_6_Q,
      LO => N9
    );
  filtro_fir_mac_sal_sum_6_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_5_cyo,
      DI => reg_acu(6),
      S => N9,
      O => filtro_fir_mac_sal_sum_6_cyo
    );
  filtro_fir_mac_sal_sum_6_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_5_cyo,
      LI => N9,
      O => sal_sum(6)
    );
  filtro_fir_mac_sal_sum_7_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(7),
      I1 => sal_mult_7_Q,
      LO => N10
    );
  filtro_fir_mac_sal_sum_7_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_6_cyo,
      DI => reg_acu(7),
      S => N10,
      O => filtro_fir_mac_sal_sum_7_cyo
    );
  filtro_fir_mac_sal_sum_7_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_6_cyo,
      LI => N10,
      O => sal_sum(7)
    );
  filtro_fir_mac_sal_sum_8_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(8),
      I1 => sal_mult_8_Q,
      LO => N11
    );
  filtro_fir_mac_sal_sum_8_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_7_cyo,
      DI => reg_acu(8),
      S => N11,
      O => filtro_fir_mac_sal_sum_8_cyo
    );
  filtro_fir_mac_sal_sum_8_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_7_cyo,
      LI => N11,
      O => sal_sum(8)
    );
  filtro_fir_mac_sal_sum_9_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(9),
      I1 => sal_mult_9_Q,
      LO => N12
    );
  filtro_fir_mac_sal_sum_9_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_8_cyo,
      DI => reg_acu(9),
      S => N12,
      O => filtro_fir_mac_sal_sum_9_cyo
    );
  filtro_fir_mac_sal_sum_9_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_8_cyo,
      LI => N12,
      O => sal_sum(9)
    );
  filtro_fir_mac_sal_sum_10_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(10),
      I1 => sal_mult_10_Q,
      LO => N13
    );
  filtro_fir_mac_sal_sum_10_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_9_cyo,
      DI => reg_acu(10),
      S => N13,
      O => filtro_fir_mac_sal_sum_10_cyo
    );
  filtro_fir_mac_sal_sum_10_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_9_cyo,
      LI => N13,
      O => sal_sum(10)
    );
  filtro_fir_mac_sal_sum_11_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(11),
      I1 => sal_mult_11_Q,
      LO => N14
    );
  filtro_fir_mac_sal_sum_11_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_10_cyo,
      DI => reg_acu(11),
      S => N14,
      O => filtro_fir_mac_sal_sum_11_cyo
    );
  filtro_fir_mac_sal_sum_11_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_10_cyo,
      LI => N14,
      O => sal_sum(11)
    );
  filtro_fir_mac_sal_sum_12_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(12),
      I1 => sal_mult_12_Q,
      LO => N15
    );
  filtro_fir_mac_sal_sum_12_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_11_cyo,
      DI => reg_acu(12),
      S => N15,
      O => filtro_fir_mac_sal_sum_12_cyo
    );
  filtro_fir_mac_sal_sum_12_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_11_cyo,
      LI => N15,
      O => sal_sum(12)
    );
  filtro_fir_mac_sal_sum_13_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(13),
      I1 => sal_mult_13_Q,
      LO => N16
    );
  filtro_fir_mac_sal_sum_13_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_12_cyo,
      DI => reg_acu(13),
      S => N16,
      O => filtro_fir_mac_sal_sum_13_cyo
    );
  filtro_fir_mac_sal_sum_13_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_12_cyo,
      LI => N16,
      O => sal_sum(13)
    );
  filtro_fir_mac_sal_sum_14_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(14),
      I1 => sal_mult_14_Q,
      LO => N17
    );
  filtro_fir_mac_sal_sum_14_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_13_cyo,
      DI => reg_acu(14),
      S => N17,
      O => filtro_fir_mac_sal_sum_14_cyo
    );
  filtro_fir_mac_sal_sum_14_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_13_cyo,
      LI => N17,
      O => sal_sum(14)
    );
  filtro_fir_mac_sal_sum_15_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(15),
      I1 => sal_mult_15_Q,
      LO => N18
    );
  filtro_fir_mac_sal_sum_15_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_14_cyo,
      DI => reg_acu(15),
      S => N18,
      O => filtro_fir_mac_sal_sum_15_cyo
    );
  filtro_fir_mac_sal_sum_15_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_14_cyo,
      LI => N18,
      O => sal_sum(15)
    );
  filtro_fir_mac_sal_sum_16_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_15_cyo,
      DI => N0,
      S => reg_acu_16_rt,
      O => filtro_fir_mac_sal_sum_16_cyo
    );
  filtro_fir_mac_sal_sum_16_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_15_cyo,
      LI => reg_acu_16_rt,
      O => sal_sum(16)
    );
  filtro_fir_mac_sal_sum_17_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_16_cyo,
      DI => N0,
      S => reg_acu_17_rt,
      O => filtro_fir_mac_sal_sum_17_cyo
    );
  filtro_fir_mac_sal_sum_17_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_16_cyo,
      LI => reg_acu_17_rt,
      O => sal_sum(17)
    );
  filtro_fir_mac_sal_sum_18_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_17_cyo,
      DI => N0,
      S => reg_acu_18_rt,
      O => filtro_fir_mac_sal_sum_18_cyo
    );
  filtro_fir_mac_sal_sum_18_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_17_cyo,
      LI => reg_acu_18_rt,
      O => sal_sum(18)
    );
  Mmult_sal_mult_inst_cy_64_9 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_63,
      DI => N0,
      S => Mmult_sal_mult_inst_lut2_38_rt,
      O => Mmult_sal_mult_inst_cy_64
    );
  Mmult_sal_mult_inst_sum_64 : XORCY
    port map (
      CI => Mmult_sal_mult_inst_cy_61,
      LI => Mmult_sal_mult_inst_lut2_36_rt,
      O => sal_mult_12_Q
    );
  Mmult_sal_mult_inst_lut2_01 : LUT2_L
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => salida_rom_0_Q,
      I1 => sal_mux(0),
      LO => Mmult_sal_mult_inst_lut2_0
    );
  Mmult_sal_mult_inst_multand_0_10 : MULT_AND
    port map (
      I0 => salida_rom_0_Q,
      I1 => sal_mux(0),
      LO => Mmult_sal_mult_inst_multand_0
    );
  Mmult_sal_mult_inst_cy_0_11 : MUXCY
    port map (
      CI => N0,
      DI => Mmult_sal_mult_inst_multand_0,
      S => Mmult_sal_mult_inst_lut2_0,
      O => Mmult_sal_mult_inst_cy_0
    );
  salida_1_OBUF : OBUF
    port map (
      I => registro_salida_M(1),
      O => salida(1)
    );
  Mmult_sal_mult_inst_lut4_01 : LUT4_L
    generic map(
      INIT => X"6AC0"
    )
    port map (
      I0 => sal_mux(0),
      I1 => sal_mux(1),
      I2 => salida_rom_0_Q,
      I3 => salida_rom_5_1,
      LO => Mmult_sal_mult_inst_lut4_0
    );
  Mmult_sal_mult_inst_multand_1_12 : MULT_AND
    port map (
      I0 => salida_rom_0_Q,
      I1 => sal_mux(1),
      LO => Mmult_sal_mult_inst_multand_1
    );
  Mmult_sal_mult_inst_cy_1_13 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_0,
      DI => Mmult_sal_mult_inst_multand_1,
      S => Mmult_sal_mult_inst_lut4_0,
      O => Mmult_sal_mult_inst_cy_1
    );
  Mmult_sal_mult_inst_sum_1 : XORCY
    port map (
      CI => Mmult_sal_mult_inst_cy_0,
      LI => Mmult_sal_mult_inst_lut4_0,
      O => sal_mult_1_Q
    );
  Mmult_sal_mult_inst_lut4_110 : LUT4_L
    generic map(
      INIT => X"6AC0"
    )
    port map (
      I0 => sal_mux(1),
      I1 => sal_mux(2),
      I2 => salida_rom_0_Q,
      I3 => salida_rom_5_1,
      LO => Mmult_sal_mult_inst_lut4_1
    );
  Mmult_sal_mult_inst_multand_2_14 : MULT_AND
    port map (
      I0 => salida_rom_0_Q,
      I1 => sal_mux(2),
      LO => Mmult_sal_mult_inst_multand_2
    );
  Mmult_sal_mult_inst_cy_2_15 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_1,
      DI => Mmult_sal_mult_inst_multand_2,
      S => Mmult_sal_mult_inst_lut4_1,
      O => Mmult_sal_mult_inst_cy_2
    );
  Mmult_sal_mult_inst_sum_2 : XORCY
    port map (
      CI => Mmult_sal_mult_inst_cy_1,
      LI => Mmult_sal_mult_inst_lut4_1,
      O => Mmult_sal_mult_N3
    );
  Mmult_sal_mult_inst_lut4_28 : LUT4_L
    generic map(
      INIT => X"6AC0"
    )
    port map (
      I0 => sal_mux(2),
      I1 => sal_mux(3),
      I2 => salida_rom_0_Q,
      I3 => salida_rom_5_1,
      LO => Mmult_sal_mult_inst_lut4_2
    );
  Mmult_sal_mult_inst_multand_3_16 : MULT_AND
    port map (
      I0 => salida_rom_0_Q,
      I1 => sal_mux(3),
      LO => Mmult_sal_mult_inst_multand_3
    );
  Mmult_sal_mult_inst_cy_3_17 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_2,
      DI => Mmult_sal_mult_inst_multand_3,
      S => Mmult_sal_mult_inst_lut4_2,
      O => Mmult_sal_mult_inst_cy_3
    );
  Mmult_sal_mult_inst_sum_3 : XORCY
    port map (
      CI => Mmult_sal_mult_inst_cy_2,
      LI => Mmult_sal_mult_inst_lut4_2,
      O => Mmult_sal_mult_N4
    );
  Mmult_sal_mult_inst_lut4_31 : LUT4_L
    generic map(
      INIT => X"6AC0"
    )
    port map (
      I0 => sal_mux(3),
      I1 => sal_mux(4),
      I2 => salida_rom_0_Q,
      I3 => salida_rom_5_1,
      LO => Mmult_sal_mult_inst_lut4_3
    );
  Mmult_sal_mult_inst_multand_4_18 : MULT_AND
    port map (
      I0 => salida_rom_0_Q,
      I1 => sal_mux(4),
      LO => Mmult_sal_mult_inst_multand_4
    );
  Mmult_sal_mult_inst_cy_4_19 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_3,
      DI => Mmult_sal_mult_inst_multand_4,
      S => Mmult_sal_mult_inst_lut4_3,
      O => Mmult_sal_mult_inst_cy_4
    );
  Mmult_sal_mult_inst_sum_4 : XORCY
    port map (
      CI => Mmult_sal_mult_inst_cy_3,
      LI => Mmult_sal_mult_inst_lut4_3,
      O => Mmult_sal_mult_N5
    );
  Mmult_sal_mult_inst_lut4_41 : LUT4_L
    generic map(
      INIT => X"6AC0"
    )
    port map (
      I0 => sal_mux(4),
      I1 => sal_mux(5),
      I2 => salida_rom_0_Q,
      I3 => salida_rom_5_1,
      LO => Mmult_sal_mult_inst_lut4_4
    );
  Mmult_sal_mult_inst_multand_5_20 : MULT_AND
    port map (
      I0 => salida_rom_0_Q,
      I1 => sal_mux(5),
      LO => Mmult_sal_mult_inst_multand_5
    );
  Mmult_sal_mult_inst_cy_5_21 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_4,
      DI => Mm