filtro_fir_mac_synthesis.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

  count_aux_0_7 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_1,
      I1 => registro0_M(1),
      I2 => registro1_M(1),
      LO => MUX_BLOCK_N7
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_2 : MUXF5
    port map (
      I0 => MUX_BLOCK_N7,
      I1 => MUX_BLOCK_N6,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF53
    );
  Mmux_sal_mux_sal_mux_0_sal_mux_0_Q : MUXF6
    port map (
      I0 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF53,
      I1 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF52,
      S => count_aux(2),
      O => sal_mux(1)
    );
  count_aux_0_8 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_02,
      I1 => registro6_M(2),
      I2 => registro7_M(2),
      LO => MUX_BLOCK_N8
    );
  count_aux_0_9 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_02,
      I1 => registro4_M(2),
      I2 => registro5_M(2),
      LO => MUX_BLOCK_N9
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_3 : MUXF5
    port map (
      I0 => MUX_BLOCK_N9,
      I1 => MUX_BLOCK_N8,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF54
    );
  count_aux_0_10 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_02,
      I1 => registro2_M(2),
      I2 => registro3_M(2),
      LO => MUX_BLOCK_N10
    );
  count_aux_0_11 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_02,
      I1 => registro0_M(2),
      I2 => registro1_M(2),
      LO => MUX_BLOCK_N111
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_4 : MUXF5
    port map (
      I0 => MUX_BLOCK_N111,
      I1 => MUX_BLOCK_N10,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF55
    );
  Mmux_sal_mux_sal_mux_0_sal_mux_0_rn_0 : MUXF6
    port map (
      I0 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF55,
      I1 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF54,
      S => count_aux(2),
      O => sal_mux(2)
    );
  count_aux_0_12 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_3,
      I1 => registro6_M(3),
      I2 => registro7_M(3),
      LO => MUX_BLOCK_N12
    );
  count_aux_0_13 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_3,
      I1 => registro4_M(3),
      I2 => registro5_M(3),
      LO => MUX_BLOCK_N13
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_5 : MUXF5
    port map (
      I0 => MUX_BLOCK_N13,
      I1 => MUX_BLOCK_N12,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF56
    );
  count_aux_0_14 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_02,
      I1 => registro2_M(3),
      I2 => registro3_M(3),
      LO => MUX_BLOCK_N14
    );
  count_aux_0_15 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_02,
      I1 => registro0_M(3),
      I2 => registro1_M(3),
      LO => MUX_BLOCK_N15
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_6 : MUXF5
    port map (
      I0 => MUX_BLOCK_N15,
      I1 => MUX_BLOCK_N14,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF57
    );
  Mmux_sal_mux_sal_mux_0_sal_mux_0_rn_1 : MUXF6
    port map (
      I0 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF57,
      I1 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF56,
      S => count_aux(2),
      O => sal_mux(3)
    );
  count_aux_0_16 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_3,
      I1 => registro6_M(4),
      I2 => registro7_M(4),
      LO => MUX_BLOCK_N16
    );
  count_aux_0_17 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_3,
      I1 => registro4_M(4),
      I2 => registro5_M(4),
      LO => MUX_BLOCK_N17
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_7 : MUXF5
    port map (
      I0 => MUX_BLOCK_N17,
      I1 => MUX_BLOCK_N16,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF58
    );
  count_aux_0_18 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_3,
      I1 => registro2_M(4),
      I2 => registro3_M(4),
      LO => MUX_BLOCK_N18
    );
  count_aux_0_19 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_02,
      I1 => registro0_M(4),
      I2 => registro1_M(4),
      LO => MUX_BLOCK_N19
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_8 : MUXF5
    port map (
      I0 => MUX_BLOCK_N19,
      I1 => MUX_BLOCK_N18,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF59
    );
  Mmux_sal_mux_sal_mux_0_sal_mux_0_rn_2 : MUXF6
    port map (
      I0 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF59,
      I1 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF58,
      S => count_aux(2),
      O => sal_mux(4)
    );
  count_aux_0_20 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_4,
      I1 => registro6_M(5),
      I2 => registro7_M(5),
      LO => MUX_BLOCK_N20
    );
  count_aux_0_21 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_4,
      I1 => registro4_M(5),
      I2 => registro5_M(5),
      LO => MUX_BLOCK_N21
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_9 : MUXF5
    port map (
      I0 => MUX_BLOCK_N21,
      I1 => MUX_BLOCK_N20,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF510
    );
  count_aux_0_22 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_3,
      I1 => registro2_M(5),
      I2 => registro3_M(5),
      LO => MUX_BLOCK_N22
    );
  count_aux_0_23 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_3,
      I1 => registro0_M(5),
      I2 => registro1_M(5),
      LO => MUX_BLOCK_N23
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_10 : MUXF5
    port map (
      I0 => MUX_BLOCK_N23,
      I1 => MUX_BLOCK_N22,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF511
    );
  Mmux_sal_mux_sal_mux_0_sal_mux_0_rn_3 : MUXF6
    port map (
      I0 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF511,
      I1 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF510,
      S => count_aux(2),
      O => sal_mux(5)
    );
  count_aux_0_24 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_4,
      I1 => registro6_M(6),
      I2 => registro7_M(6),
      LO => MUX_BLOCK_N24
    );
  count_aux_0_25 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_4,
      I1 => registro4_M(6),
      I2 => registro5_M(6),
      LO => MUX_BLOCK_N25
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_11 : MUXF5
    port map (
      I0 => MUX_BLOCK_N25,
      I1 => MUX_BLOCK_N24,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF512
    );
  count_aux_0_26 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_4,
      I1 => registro2_M(6),
      I2 => registro3_M(6),
      LO => MUX_BLOCK_N26
    );
  count_aux_0_27 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_3,
      I1 => registro0_M(6),
      I2 => registro1_M(6),
      LO => MUX_BLOCK_N27
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_12 : MUXF5
    port map (
      I0 => MUX_BLOCK_N27,
      I1 => MUX_BLOCK_N26,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF513
    );
  Mmux_sal_mux_sal_mux_0_sal_mux_0_rn_4 : MUXF6
    port map (
      I0 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF513,
      I1 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF512,
      S => count_aux(2),
      O => sal_mux(6)
    );
  count_aux_0_28 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_4,
      I1 => registro6_M(7),
      I2 => registro7_M(7),
      LO => MUX_BLOCK_N28
    );
  count_aux_0_29 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_4,
      I1 => registro4_M(7),
      I2 => registro5_M(7),
      LO => MUX_BLOCK_N29
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_13 : MUXF5
    port map (
      I0 => MUX_BLOCK_N29,
      I1 => MUX_BLOCK_N28,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF514
    );
  count_aux_0_30 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_4,
      I1 => registro2_M(7),
      I2 => registro3_M(7),
      LO => MUX_BLOCK_N30
    );
  count_aux_0_31 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_4,
      I1 => registro0_M(7),
      I2 => registro1_M(7),
      LO => MUX_BLOCK_N31
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_14 : MUXF5
    port map (
      I0 => MUX_BLOCK_N31,
      I1 => MUX_BLOCK_N30,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF515
    );
  Mmux_sal_mux_sal_mux_0_sal_mux_0_rn_5 : MUXF6
    port map (
      I0 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF515,
      I1 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF514,
      S => count_aux(2),
      O => sal_mux(7)
    );
  Mmult_sal_mult_inst_cy_59_7 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_58,
      DI => Mmult_sal_mult_N46,
      S => Mmult_sal_mult_inst_lut2_33,
      O => Mmult_sal_mult_inst_cy_59
    );
  Mmult_sal_mult_inst_sum_63 : XORCY
    port map (
      CI => Mmult_sal_mult_inst_cy_60,
      LI => Mmult_sal_mult_inst_lut2_35,
      O => sal_mult_11_Q
    );
  Mmult_sal_mult_inst_cy_61_8 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_60,
      DI => Mmult_sal_mult_N48,
      S => Mmult_sal_mult_inst_lut2_35,
      O => Mmult_sal_mult_inst_cy_61
    );
  Mmult_sal_mult_inst_lut2_351 : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => Mmult_sal_mult_N48,
      I1 => Mmult_sal_mult_N70,
      LO => Mmult_sal_mult_inst_lut2_35
    );
  Mmult_sal_mult_inst_sum_62 : XORCY
    port map (
      CI => Mmult_sal_mult_inst_cy_59,
      LI => Mmult_sal_mult_inst_lut2_34,
      O => sal_mult_10_Q
    );
  filtro_fir_mac_sal_sum_2_lut : LUT4_L
    generic map(
      INIT => X"965A"
    )
    port map (
      I0 => reg_acu(2),
      I1 => salida_rom_5_Q,
      I2 => Mmult_sal_mult_N3,
      I3 => sal_mux(0),
      LO => N5
    );
  filtro_fir_mac_sal_sum_0_cy : MUXCY
    port map (
      CI => N0,
      DI => reg_acu(0),
      S => sal_sum(0),
      O => filtro_fir_mac_sal_sum_0_cyo
    );
  salida_0_OBUF : OBUF
    port map (
      I => registro_salida_M(0),
      O => salida(0)
    );
  filtro_fir_mac_sal_sum_1_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(1),
      I1 => sal_mult_1_Q,
      LO => N4
    );
  filtro_fir_mac_sal_sum_1_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_0_cyo,
      DI => reg_acu(1),
      S => N4,
      O => filtro_fir_mac_sal_sum_1_cyo
    );
  filtro_fir_mac_sal_sum_1_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_0_cyo,
      LI => N4,
      O => sal_sum(1)
    );
  filtro_fir_mac_sal_sum_4_lut : LUT4_L
    generic map(
      INIT => X"965A"
    )
    port map (
      I0 => reg_acu(4),
      I1 => salida_rom_5_Q,
      I2 => Mmult_sal_mult_N41,
      I3 => sal_mux(0),
      LO => N7
    );
  filtro_fir_mac_sal_sum_2_cy : MUXCY
    port map (
      CI => filtro_fir_mac_sal_sum_1_cyo,
      DI => reg_acu(2),
      S => N5,
      O => filtro_fir_mac_sal_sum_2_cyo
    );
  filtro_fir_mac_sal_sum_2_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_1_cyo,
      LI => N5,
      O => sal_sum(2)
    );
  filtro_fir_mac_sal_sum_3_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_acu(3),
      I1 => sal_mult_3_Q,