filtro_fir_mac_synthesis.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

    );
  registro3_M_1 : FDCE
    port map (
      D => registro2_M(1),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro3_M(1)
    );
  registro3_M_2 : FDCE
    port map (
      D => registro2_M(2),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro3_M(2)
    );
  registro3_M_3 : FDCE
    port map (
      D => registro2_M(3),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro3_M(3)
    );
  registro3_M_4 : FDCE
    port map (
      D => registro2_M(4),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro3_M(4)
    );
  registro3_M_5 : FDCE
    port map (
      D => registro2_M(5),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro3_M(5)
    );
  registro2_M_7 : FDCE
    port map (
      D => registro1_M(7),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro2_M(7)
    );
  registro2_M_0 : FDCE
    port map (
      D => registro1_M(0),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro2_M(0)
    );
  registro2_M_1 : FDCE
    port map (
      D => registro1_M(1),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro2_M(1)
    );
  registro2_M_2 : FDCE
    port map (
      D => registro1_M(2),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro2_M(2)
    );
  registro2_M_3 : FDCE
    port map (
      D => registro1_M(3),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro2_M(3)
    );
  registro2_M_4 : FDCE
    port map (
      D => registro1_M(4),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro2_M(4)
    );
  registro2_M_5 : FDCE
    port map (
      D => registro1_M(5),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro2_M(5)
    );
  registro1_M_7 : FDCE
    port map (
      D => registro0_M(7),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro1_M(7)
    );
  registro1_M_0 : FDCE
    port map (
      D => registro0_M(0),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro1_M(0)
    );
  registro1_M_1 : FDCE
    port map (
      D => registro0_M(1),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro1_M(1)
    );
  registro1_M_2 : FDCE
    port map (
      D => registro0_M(2),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro1_M(2)
    );
  registro1_M_3 : FDCE
    port map (
      D => registro0_M(3),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro1_M(3)
    );
  registro1_M_4 : FDCE
    port map (
      D => registro0_M(4),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro1_M(4)
    );
  registro1_M_5 : FDCE
    port map (
      D => registro0_M(5),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro1_M(5)
    );
  registro0_M_7 : FDCE
    port map (
      D => entrada_7_IBUF,
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro0_M(7)
    );
  registro0_M_0 : FDCE
    port map (
      D => entrada_0_IBUF,
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro0_M(0)
    );
  registro0_M_1 : FDCE
    port map (
      D => entrada_1_IBUF,
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro0_M(1)
    );
  registro0_M_2 : FDCE
    port map (
      D => entrada_2_IBUF,
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro0_M(2)
    );
  registro0_M_3 : FDCE
    port map (
      D => entrada_3_IBUF,
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro0_M(3)
    );
  registro0_M_4 : FDCE
    port map (
      D => entrada_4_IBUF,
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro0_M(4)
    );
  registro0_M_5 : FDCE
    port map (
      D => entrada_5_IBUF,
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro0_M(5)
    );
  registro_salida_M_19 : FDCE
    port map (
      D => sal_sum(19),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(19)
    );
  registro_salida_M_0 : FDCE
    port map (
      D => sal_sum(0),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(0)
    );
  registro_salida_M_1 : FDCE
    port map (
      D => sal_sum(1),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(1)
    );
  registro_salida_M_2 : FDCE
    port map (
      D => sal_sum(2),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(2)
    );
  registro_salida_M_3 : FDCE
    port map (
      D => sal_sum(3),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(3)
    );
  registro_salida_M_4 : FDCE
    port map (
      D => sal_sum(4),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(4)
    );
  registro_salida_M_5 : FDCE
    port map (
      D => sal_sum(5),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(5)
    );
  registro_salida_M_6 : FDCE
    port map (
      D => sal_sum(6),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(6)
    );
  registro_salida_M_7 : FDCE
    port map (
      D => sal_sum(7),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(7)
    );
  registro_salida_M_8 : FDCE
    port map (
      D => sal_sum(8),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(8)
    );
  registro_salida_M_9 : FDCE
    port map (
      D => sal_sum(9),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(9)
    );
  registro_salida_M_10 : FDCE
    port map (
      D => sal_sum(10),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(10)
    );
  registro_salida_M_11 : FDCE
    port map (
      D => sal_sum(11),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(11)
    );
  registro_salida_M_12 : FDCE
    port map (
      D => sal_sum(12),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(12)
    );
  registro_salida_M_13 : FDCE
    port map (
      D => sal_sum(13),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(13)
    );
  registro_salida_M_14 : FDCE
    port map (
      D => sal_sum(14),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(14)
    );
  registro_salida_M_15 : FDCE
    port map (
      D => sal_sum(15),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(15)
    );
  registro_salida_M_16 : FDCE
    port map (
      D => sal_sum(16),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(16)
    );
  registro_salida_M_17 : FDCE
    port map (
      D => sal_sum(17),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(17)
    );
  Mmult_sal_mult_inst_cy_60_2 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_59,
      DI => Mmult_sal_mult_N47,
      S => Mmult_sal_mult_inst_lut2_34,
      O => Mmult_sal_mult_inst_cy_60
    );
  count_aux_Madd_n0000_Mxor_Result_2_Result1 : LUT3
    generic map(
      INIT => X"78"
    )
    port map (
      I0 => count_aux(0),
      I1 => count_aux(1),
      I2 => count_aux(2),
      O => count_aux_n0000(2)
    );
  salida_rom_5_1_3 : LUT3
    generic map(
      INIT => X"81"
    )
    port map (
      I0 => count_aux_0_1,
      I1 => count_aux_1_1,
      I2 => count_aux(2),
      O => salida_rom_5_Q
    );
  Mmult_sal_mult_inst_lut2_331 : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => Mmult_sal_mult_N46,
      I1 => Mmult_sal_mult_N68,
      LO => Mmult_sal_mult_inst_lut2_33
    );
  Mmult_sal_mult_inst_sum_61 : XORCY
    port map (
      CI => Mmult_sal_mult_inst_cy_58,
      LI => Mmult_sal_mult_inst_lut2_33,
      O => sal_mult_9_Q
    );
  count_aux_0_Q : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_1,
      I1 => registro6_M(0),
      I2 => registro7_M(0),
      LO => MUX_BLOCK_N01
    );
  count_aux_0_1_4 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_1,
      I1 => registro4_M(0),
      I2 => registro5_M(0),
      LO => MUX_BLOCK_N11
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1 : MUXF5
    port map (
      I0 => MUX_BLOCK_N11,
      I1 => MUX_BLOCK_N01,
      S => count_aux_1_1,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF5
    );
  count_aux_0_2 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_1,
      I1 => registro2_M(0),
      I2 => registro3_M(0),
      LO => MUX_BLOCK_N2
    );
  count_aux_0_3_5 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_1,
      I1 => registro0_M(0),
      I2 => registro1_M(0),
      LO => MUX_BLOCK_N3
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_0 : MUXF5
    port map (
      I0 => MUX_BLOCK_N3,
      I1 => MUX_BLOCK_N2,
      S => count_aux_1_1,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF51
    );
  Mmux_sal_mux_sal_mux_0_Q : MUXF6
    port map (
      I0 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF51,
      I1 => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF5,
      S => count_aux(2),
      O => sal_mux(0)
    );
  count_aux_0_4_6 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_1,
      I1 => registro6_M(1),
      I2 => registro7_M(1),
      LO => MUX_BLOCK_N4
    );
  count_aux_0_5 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_1,
      I1 => registro4_M(1),
      I2 => registro5_M(1),
      LO => MUX_BLOCK_N5
    );
  count_aux_1_mmx_out1_count_aux_1_mmx_out1_rn_1 : MUXF5
    port map (
      I0 => MUX_BLOCK_N5,
      I1 => MUX_BLOCK_N4,
      S => count_aux_1_2,
      O => MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF52
    );
  count_aux_0_6 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => count_aux_0_1,
      I1 => registro2_M(1),
      I2 => registro3_M(1),
      LO => MUX_BLOCK_N6
    );